diff --git a/fast-servo/linien-gateware/cores/adc.py b/fast-servo/linien-gateware/cores/adc.py
index 1d3ecf3..bae6dff 100644
--- a/fast-servo/linien-gateware/cores/adc.py
+++ b/fast-servo/linien-gateware/cores/adc.py
@@ -135,7 +135,7 @@ class ADC(Module, AutoCSR):
         self.s_frame = Signal(4)
         self.s_frame_cdc = Signal(4)
 
-        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 2))
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 4))
         self.comb += [
             self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)),
             self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")),
diff --git a/fast-servo/linien-gateware/cores/dac.py b/fast-servo/linien-gateware/cores/dac.py
index ab9b8f0..26cd3d9 100644
--- a/fast-servo/linien-gateware/cores/dac.py
+++ b/fast-servo/linien-gateware/cores/dac.py
@@ -42,7 +42,7 @@ class DAC(Module, AutoCSR):
         self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
         platform.add_period_constraint(dac_pads.dclkio, 10.0)
 
-        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 2))
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 4))
         self.comb += [
             self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])),
             self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),