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kirdy
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base: linuswck:47a30da9b160e125b64cbf0d6730ef053de4fb98
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linuswck:rev0_3
linuswck:master
sinara-hw:master
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compare: linuswck:fbe79e72475e7d0b4e3a31f41ba8742e14375364
Branches Tags
linuswck:rev0_3
linuswck:master
sinara-hw:master

19 Commits
47a30da9b1 ... fbe79e7247

Author SHA1 Message Date
linuswck fbe79e7247 Cleanup and Update Modification Date 2023-11-27 17:40:03 +08:00
linuswck bc2a44af86 Scripts: Comment Filed is included in the BOM 2023-11-27 17:37:52 +08:00
linuswck 347cc482f9 3D: Update 3D models of KIrdy LD Adapter 2023-11-27 17:37:52 +08:00
linuswck 395433176c sch, pcb: Add 12V & Mounting holes to MCU EXT HDR 2023-11-27 17:37:52 +08:00
linuswck 83506fd3c6 sch, pcb: add tantalum C0G Caps for 8V out LT3045 2023-11-27 17:37:52 +08:00
linuswck f24f037348 sch, pcb: Change kirdy LD adpter connectors 
- Add two extra mounting holes for kirdy LD adapter
- Update kirdy LD adapter 3D model
- Update the PCB layout accordingly
 2023-11-27 17:37:52 +08:00
linuswck 95494ee031 sch, pcb: Add LPF and Buffer for TEC VREF 2023-11-27 17:37:52 +08:00
linuswck e7a7eee202 sch, pcb: Remove X7R, X5R at input LT304x 
- Reduce the number of Tantalum Capacitor Used
- Replace some non critical ones with Electrolytic Caps
 2023-11-27 17:37:52 +08:00
linuswck f29c460e72 Add: Footprints and Step Model for Caps 
- SMD ELEC: 865080345012
- SMD C0G Ceramic GRMJN65C1H104JE01J
 2023-11-27 17:37:52 +08:00
linuswck 5f7743698e pcb: Add reference designators for connectors, SWs 
- SMA Connector, USB Type C, Power Jack, RJ45
- MCU Programming Headers and Boot 0 Headers
- Termination Resistor SW, Modulation Depth SW
 2023-11-27 17:37:52 +08:00
linuswck 43903708c3 sch, pcb: Replace FB of -6V +15V LDO with inductor 
- Build a Pi LPF on the input side
 2023-11-27 17:37:52 +08:00
linuswck 24637b4216 sch, pcb: Add alternate footprint for LTC6655 Vref 2023-11-27 17:37:52 +08:00
linuswck 2cbab29c4e sch, pcb: Add LEDs and TPs to Critical Power Rails 2023-11-27 17:37:52 +08:00
linuswck c59eccaa7d sch, pcb: add 0R for TEC Vref Ouput 
- For debugging if needed
 2023-11-27 17:37:52 +08:00
linuswck db54e6cfa8 sch, pcb:Edit PCB shape for connectors to protrude 
- Connectors now protrude the front panel
- Align the connectors by the outline generated from 3D Model
- Update the front panel symbol to include the two mounting holes
 2023-11-27 17:37:52 +08:00
linuswck e0989a61f2 Add Front Panel FreeCAD Assembly 
- Static Handle
- PCB Brackets
- Kirdy Front Panel Cutout
 2023-11-27 17:37:47 +08:00
linuswck 13a90dd642 3D_Model: Update 204-121ST 2023-11-21 11:46:48 +08:00
linuswck b901f84d0a sch, pcb: Add PWR, POE_PWR netclasses 2023-11-21 11:46:46 +08:00
linuswck 20198f5eab drc: Check PWR nets clearance on pri and sec sides 
- Pri: PoE PWR nets
- Sec: PWR nets like GND, 3V3 etc
 2023-11-21 11:46:39 +08:00
31 changed files with 244596 additions and 94540 deletions
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3561
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asupply.kicad_sch
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driveStage.kicad_sch
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eth.kicad_sch
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@ -6,7 +6,7 @@
(title_block
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(date "2023-11-09")
(date "2023-11-27")
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(company "M-Labs Limited")
(comment 1 "Linus Woo Chun Kit")
@ -1849,7 +1849,7 @@
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(property "Value" "+3V3" (at 335.28 184.1499 90)
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5
kirdy.kicad_dru Normal file
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@ -0,0 +1,5 @@
(version 1)
(rule "PoE PWR Clearance Between GND and PoE AC Input"
(constraint clearance (min 1.0mm))
(condition " A.NetClass != B.NetClass && A.NetClass == 'PWR' && B.NetClass == 'POE_PWR' " ))

84725
kirdy.kicad_pcb
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63
kirdy.kicad_pro
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@ -102,9 +102,9 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_edge_clearance": "ignore",
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
@ -127,7 +127,7 @@
"min_clearance": 0.08889999999999999,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.254,
"min_hole_clearance": 0.19999999999999998,
"min_hole_to_hole": 0.254,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
@ -454,6 +454,40 @@
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.0889,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "POE_PWR",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.0889,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
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"microvia_drill": 0.1,
"name": "PWR",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
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}
],
"meta": {
@ -461,7 +495,28 @@
},
"net_colors": null,
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"netclass_patterns": [
{
"netclass": "POE_PWR",
"pattern": "/*/POE_VC*"
},
{
"netclass": "PWR",
"pattern": "+*"
},
{
"netclass": "PWR",
"pattern": "-*"
},
{
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"pattern": "GND"
},
{
"netclass": "PWR",
"pattern": "/*/+*"
}
]
},
"pcbnew": {
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530
kirdy.kicad_sch
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@ -6,7 +6,7 @@
(title_block
(title "Kirdy")
(date "2023-11-09")
(date "2023-11-27")
(rev "r0_3")
(company "M-Labs Limited")
(comment 1 "Linus Woo Chun Kit")
@ -52,35 +52,6 @@
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)
)
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6950
kirdy.pretty/Panel_Cutout.kicad_mod Normal file
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59
kirdy.pretty/SOP65P490X110-8N.kicad_mod Normal file
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(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ef507180-e11a-4baf-b722-4a07323f1244))
(fp_line (start 1.5 1.5) (end -1.5 1.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4ed68c10-e7d9-452d-8351-d4882ce3cbd2))
(pad "1" smd rect (at -2.212 -0.975 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5113c7d7-fd53-4153-ba0d-47681d010562))
(pad "2" smd rect (at -2.212 -0.325 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f058ff38-2022-4211-9be2-09eb78833ef3))
(pad "3" smd rect (at -2.212 0.325 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d1421195-b43f-4c47-9c39-21a06e9ee94f))
(pad "4" smd rect (at -2.212 0.975 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d5463418-d1f2-47e1-a0a7-2bbc40dc9458))
(pad "5" smd rect (at 2.212 0.975 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 231b49c1-61ee-432c-9aa6-89f33929c85c))
(pad "6" smd rect (at 2.212 0.325 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b8784-17a7-4853-883d-fea3fbaa0533))
(pad "7" smd rect (at 2.212 -0.325 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 835b7d96-00c8-4f0c-829f-b0474a4c52fb))
(pad "8" smd rect (at 2.212 -0.975 90) (size 0.45 1.425) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 83a79ab8-1d1b-42bc-80f4-7723b7588faa))
(model "${KIPRJMOD}/kirdy.pretty/LTC6655BHMS8-4.096#PBF.stp"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

1158
mcu.kicad_sch
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7
scripts/generate_bom_from_xml.py
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@ -6,7 +6,7 @@
The BOM does not include components with DNP or excluded from BOM field(s) checked.
Grouped By: Value, Footprint, MFR_PN, MFR_ALT
Sorted By: Ref
Fields: Ref, Value, MFR_PN, MFR_PN_ALT, Qnty, LibPart, Footprint
Fields: Ref, Value, MFR_PN, MFR_PN_ALT, Qnty, LibPart, Footprint, Comment
Command line:
python "pathToFile/generate_bom_from_xml.py" "%I" "%O.csv"
@ -41,7 +41,7 @@ out = csv.writer(f, lineterminator='\n', delimiter=',', quotechar='\"', quoting=
out.writerow(['Source:', net.getSource()])
out.writerow(['Date:', net.getDate()])
out.writerow(['Tool:', net.getTool()])
out.writerow(['Ref', 'Value', 'MFR_PN', 'MFR_PN_ALT', 'Qnty', 'LibPart', 'Footprint'])
out.writerow(['Ref', 'Value', 'MFR_PN', 'MFR_PN_ALT', 'Qnty', 'LibPart', 'Footprint', 'Comment'])
grouped = net.groupComponents(components=net.getInterestingComponents(excludeBOM=True, DNP=True))
@ -59,4 +59,5 @@ for group in grouped:
c.getField("MFR_PN_ALT"),
len(group),
c.getLibName() + ":" + c.getPartName(),
c.getFootprint()])
c.getFootprint(),
c.getField("Comment")])

803
thermostat.kicad_sch
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2
usb.kicad_sch
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@ -6,7 +6,7 @@
(title_block
(title "USB")
(date "2023-11-09")
(date "2023-11-27")
(rev "r0_3")
(company "M-Labs Limited")
(comment 1 "Linus Woo Chun Kit")