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kirdy-firmware
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thermostat: settings obj now contains the exact filter type and val

This commit is contained in:
linuswck 2024-10-10 13:39:37 +08:00
parent 253f4410ee
commit 31e108a4b5
2 changed files with 26 additions and 16 deletions
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10
src/thermostat/ad7172/adc.rs
View File

@ -116,9 +116,11 @@ impl<SPI: SpiBus<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
} }
/// Rate is only valid with single channel enabled /// Rate is only valid with single channel enabled
pub fn get_filter_type_and_rate(&mut self, index: u8) -> Result<(FilterType, f32), SPI::Error> { pub fn get_filter_type_and_rate(&mut self, index: u8) -> Result<(FilterType, Option<SingleChODR>, Option<PostFilter>, f32), SPI::Error> {
let mut filter_type: FilterType = FilterType::Sinc5Sinc1With50hz60HzRejection; let mut filter_type: FilterType = FilterType::Sinc5Sinc1With50hz60HzRejection;
let mut rate: f32 = -1.0; let mut rate: f32 = -1.0;
let mut single_ch_odr : Option<SingleChODR> = None;
let mut post_filter: Option<PostFilter> = None;
self.read_reg(&regs::FiltCon { index }).map(|data| { self.read_reg(&regs::FiltCon { index }).map(|data| {
if data.sinc3_map() { if data.sinc3_map() {
filter_type = FilterType::Sinc3WithFineODR; filter_type = FilterType::Sinc3WithFineODR;
@ -134,6 +136,7 @@ impl<SPI: SpiBus<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
rate = -1.0; rate = -1.0;
} }
}; };
post_filter = Some(data.enh_filt())
} else if data.order() == DigitalFilterOrder::Sinc5Sinc1 { } else if data.order() == DigitalFilterOrder::Sinc5Sinc1 {
filter_type = FilterType::Sinc5Sinc1; filter_type = FilterType::Sinc5Sinc1;
match data.odr().output_rate() { match data.odr().output_rate() {
@ -144,6 +147,7 @@ impl<SPI: SpiBus<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
rate = -1.0; rate = -1.0;
} }
} }
single_ch_odr = Some(data.odr())
} else { } else {
filter_type = FilterType::Sinc3; filter_type = FilterType::Sinc3;
match data.odr().output_rate() { match data.odr().output_rate() {
@ -154,10 +158,10 @@ impl<SPI: SpiBus<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
rate = -1.0; rate = -1.0;
} }
} }
single_ch_odr = Some(data.odr())
} }
})?; })?;
Ok((filter_type, single_ch_odr, post_filter, rate))
Ok((filter_type, rate))
} }
pub fn set_sinc5_sinc1_with_50hz_60hz_rejection(&mut self, index: u8, rate: PostFilter) -> Result<(), SPI::Error> { pub fn set_sinc5_sinc1_with_50hz_60hz_rejection(&mut self, index: u8, rate: PostFilter) -> Result<(), SPI::Error> {

32
src/thermostat/thermostat.rs
View File

@ -522,12 +522,25 @@ impl Thermostat {
} }
pub fn get_settings_summary(&mut self) -> ThermostatSettingsSummary { pub fn get_settings_summary(&mut self) -> ThermostatSettingsSummary {
let temp_adc_filter_type: FilterType; let mut temp_adc_settings: TempAdcFilter = TempAdcFilter::default();
let update_rate: f32;
match self.ad7172.get_filter_type_and_rate(0) { match self.ad7172.get_filter_type_and_rate(0) {
Ok((filter_type, rate)) => { Ok((filter_type, single_ch_odr, post_filter, rate)) => {
temp_adc_filter_type = filter_type; temp_adc_settings.filter_type = filter_type;
update_rate = rate; temp_adc_settings.rate = Some(rate);
match temp_adc_settings.filter_type {
FilterType::Sinc5Sinc1 => {
temp_adc_settings.sinc5sinc1odr = single_ch_odr;
}
FilterType::Sinc3 => {
temp_adc_settings.sinc3odr = single_ch_odr;
}
FilterType::Sinc3WithFineODR => {
temp_adc_settings.sinc3fineodr = Some(rate)
}
FilterType::Sinc5Sinc1With50hz60HzRejection => {
temp_adc_settings.sinc5sinc1postfilter = post_filter
}
}
} }
Err(_) => { Err(_) => {
panic!("Cannot read ADC filter type and rate"); panic!("Cannot read ADC filter type and rate");
@ -540,14 +553,7 @@ impl Thermostat {
temperature_setpoint: self.pid_ctrl_ch0.get_pid_setpoint(), temperature_setpoint: self.pid_ctrl_ch0.get_pid_setpoint(),
tec_settings: self.get_tec_settings(), tec_settings: self.get_tec_settings(),
pid_params: self.get_pid_settings(), pid_params: self.get_pid_settings(),
temp_adc_settings: TempAdcFilter { temp_adc_settings: temp_adc_settings,
filter_type: temp_adc_filter_type,
sinc5sinc1odr: None,
sinc3odr: None,
sinc5sinc1postfilter: None,
sinc3fineodr: None,
rate: Some(update_rate),
},
temp_mon_settings: self.get_temp_mon_settings(), temp_mon_settings: self.get_temp_mon_settings(),
thermistor_params: self.get_steinhart_hart(), thermistor_params: self.get_steinhart_hart(),
} }