forked from M-Labs/artiq-zynq
74 lines
2.3 KiB
Python
Executable File
74 lines
2.3 KiB
Python
Executable File
#!/usr/bin/env python
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import argparse
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from migen import *
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zc706
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from misoc.integration import cpu_interface
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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class ZC706(SoCCore):
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def __init__(self):
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platform = zc706.Platform()
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SoCCore.__init__(self, platform=platform)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.clock_domains.cd_rtio = ClockDomain()
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self.comb += [
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self.cd_rtio.clk.eq(self.ps7.cd_sys.clk),
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self.cd_rtio.rst.eq(self.ps7.cd_sys.rst)
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]
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rtio_channels = []
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for i in range(4):
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pad = platform.request("user_led", i)
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phy = ttl_simple.InOut(pad)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.csr_devices.append("rtio")
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self.comb += self.rtio.cri.connect(self.rtio_core.cri)
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the ZC706 Zynq development kit")
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parser.add_argument("action", metavar="ACTION", nargs="*",
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default="gateware rustif".split(),
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help="actions to perform, default: %(default)s")
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args = parser.parse_args()
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soc = ZC706()
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soc.finalize()
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for action in args.action:
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if action == "gateware":
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soc.build()
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elif action == "rustif":
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write_csr_file(soc, "pl.rs")
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else:
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raise ValueError("invalid action", action)
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if __name__ == "__main__":
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main()
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