forked from M-Labs/artiq-zynq
527 lines
21 KiB
Python
Executable File
527 lines
21 KiB
Python
Executable File
#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import kasli_soc
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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import dma
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import analyzer
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import acpki
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import drtio_aux_controller
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=clk_synth_se,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=rtio_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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eem_iostandard_dict = {
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0: "LVDS_25",
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1: "LVDS_25",
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2: "LVDS",
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3: "LVDS",
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4: "LVDS",
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5: "LVDS",
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6: "LVDS",
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7: "LVDS",
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8: "LVDS_25",
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9: "LVDS_25",
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10: "LVDS",
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11: "LVDS",
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}
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def eem_iostandard(eem):
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return IOStandard(eem_iostandard_dict[eem])
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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for i in (0, 1):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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user_led = self.platform.request("user_led", i)
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk125_gtp"),
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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for i in (0, 1):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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user_led = self.platform.request("user_led", i)
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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size = coreaux.get_mem_size()
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
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self.axi2csr.register_port(coreaux.get_rx_port(), size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk125_gtp"),
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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for i in (0, 1):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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user_led = self.platform.request("user_led", i)
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[i],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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mem_size = coreaux.get_mem_size()
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tx_port = coreaux.get_tx_port()
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rx_port = coreaux.get_rx_port()
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memory_address = self.axi2csr.register_port(tx_port, mem_size)
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# rcv in upper half of the memory, thus added second
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self.axi2csr.register_port(rx_port, mem_size)
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# and registered in PS interface
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# manually, because software refers to rx/tx by halves of entire memory block, not names
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
|
bus=self.ps7.s_axi_acp,
|
|
user=self.ps7.s_axi_acp_user,
|
|
evento=self.ps7.event.o)
|
|
self.csr_devices.append("rtio")
|
|
else:
|
|
self.rustc_cfg["ki_impl"] = "csr"
|
|
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
|
|
self.csr_devices.append("rtio")
|
|
|
|
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
|
|
self.csr_devices.append("rtio_dma")
|
|
|
|
self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels)
|
|
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
|
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.drtiosat.cri],
|
|
[self.local_io.cri] + self.drtio_cri,
|
|
mode="sync", enable_routing=True)
|
|
self.csr_devices.append("cri_con")
|
|
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
|
|
|
|
self.submodules.siphaser = SiPhaser7Series(
|
|
si5324_clkin=platform.request("cdr_clk"),
|
|
rx_synchronizer=self.rx_synchronizer,
|
|
ultrascale=False,
|
|
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
|
self.csr_devices.append("siphaser")
|
|
self.rustc_cfg["has_si5324"] = None
|
|
self.rustc_cfg["has_siphaser"] = None
|
|
self.rustc_cfg["si5324_soft_reset"] = None
|
|
|
|
gtx0 = self.drtio_transceiver.gtxs[0]
|
|
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
|
|
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gtx0.txoutclk, gtx0.rxoutclk)
|
|
for gtx in self.drtio_transceiver.gtxs[1:]:
|
|
platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, gtx.rxoutclk)
|
|
|
|
if has_grabber:
|
|
self.rustc_cfg["has_grabber"] = None
|
|
self.add_csr_group("grabber", self.grabber_csr_group)
|
|
# no RTIO CRG here
|
|
|
|
|
|
def write_mem_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
f.write(cpu_interface.get_mem_rust(
|
|
soc.get_memory_regions(), soc.get_memory_groups(), None))
|
|
|
|
|
|
def write_csr_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
f.write(cpu_interface.get_csr_rust(
|
|
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
|
|
|
|
|
|
def write_rustc_cfg_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
|
|
if v is None:
|
|
f.write("{}\n".format(k))
|
|
else:
|
|
f.write("{}=\"{}\"\n".format(k, v))
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="ARTIQ device binary builder for generic Kasli-SoC systems")
|
|
parser.add_argument("-r", default=None,
|
|
help="build Rust interface into the specified file")
|
|
parser.add_argument("-c", default=None,
|
|
help="build Rust compiler configuration into the specified file")
|
|
parser.add_argument("-m", default=None,
|
|
help="build Rust memory interface into the specified file")
|
|
parser.add_argument("-g", default=None,
|
|
help="build gateware into the specified directory")
|
|
parser.add_argument("--acpki", default=False, action="store_true",
|
|
help="enable ACPKI")
|
|
parser.add_argument("description", metavar="DESCRIPTION",
|
|
help="JSON system description file")
|
|
args = parser.parse_args()
|
|
description = jsondesc.load(args.description)
|
|
|
|
if description["target"] != "kasli_soc":
|
|
raise ValueError("Description is for a different target")
|
|
|
|
if description["base"] == "standalone":
|
|
cls = GenericStandalone
|
|
elif description["base"] == "master":
|
|
cls = GenericMaster
|
|
elif description["base"] == "satellite":
|
|
cls = GenericSatellite
|
|
else:
|
|
raise ValueError("Invalid base")
|
|
|
|
soc = cls(description, acpki=args.acpki)
|
|
soc.finalize()
|
|
|
|
if args.r is not None:
|
|
write_csr_file(soc, args.r)
|
|
if args.m is not None:
|
|
write_mem_file(soc, args.m)
|
|
if args.c is not None:
|
|
write_rustc_cfg_file(soc, args.c)
|
|
if args.g is not None:
|
|
soc.build(build_dir=args.g)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|