linuswck
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

Compare commits

base: linuswck:ce909a9e0c08f040a08f2bb91aa2f7ebff240ef2
Branches Tags
linuswck:master
linuswck:gtx_clock_path_fix
linuswck:kasli_soc_demo_add_bufg_to_clk_synth
linuswck:shuttler_kasli_soc_port
linuswck:rename_drtio_transceiver_to_gt_drtio
linuswck:release-7
linuswck:release-6
M-Labs:release-7
M-Labs:release-8
M-Labs:master
M-Labs:release-6
..
compare: linuswck:a7cc4aa2806c7005030c1e0ada6ebd0d7d9d5207
Branches Tags
linuswck:gtx_clock_path_fix
linuswck:kasli_soc_demo_add_bufg_to_clk_synth
linuswck:master
linuswck:shuttler_kasli_soc_port
linuswck:rename_drtio_transceiver_to_gt_drtio
linuswck:release-7
linuswck:release-6
M-Labs:release-7
M-Labs:release-8
M-Labs:master
M-Labs:release-6

3 Commits
ce909a9e0c ... a7cc4aa280

Author SHA1 Message Date
linuswck a7cc4aa280 Firmware: Add drtio_eem.rs support 
- Port from Artiq repo
- Initialize the drtio_eem on main, rtio_clocking
- Driver for eem_transceiver
 2023-10-09 17:40:44 +08:00
linuswck 08469e46fe kasli_soc: Add support for shuttler on gateware 
- Port from artiq repo
- If shuttler is present, then enable_sys5x in clocking and add the related EEM_DRTIO gateware
 2023-10-09 17:40:44 +08:00
linuswck d4e8dd1554 zynq_clocking: add enable_sys5x option, IDELAYCTRL 
- Port from artiq repo
- If enable_sys5x,
    - add one PLL thats generate 200MHz IDELAYCTRL ref clock
    - add a IDELAYCTRL instance for EEM Serdes
    - add sys5x for EEM Serdes
 2023-10-09 17:40:35 +08:00
Show Stats Expand all files Collapse all files

Diff Content Not Available