satman: fix dma reporting wrong destination

Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>

flake.nix

@@ -123,7 +123,7 @@
         cargoLock = { 
           lockFile = src/Cargo.lock;
           outputHashes = {
-            "libasync-0.0.0" = "sha256-WvNMUekL4Elc55RdqX8XP43QPnBrK8Rbd0bsoI61E5U=";
+            "libasync-0.0.0" = "sha256-MppR7yxs3cjG7tQc82vX0MhyN71CJL2QWkM65F5hrFU=";
           };
         };
 

src/Cargo.lock

@@ -221,7 +221,7 @@ dependencies = [
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#67dbb5932fa8ff5f143983476f741f945871d286"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
@@ -253,7 +253,7 @@ dependencies = [
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#67dbb5932fa8ff5f143983476f741f945871d286"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
  "bit_field",
  "embedded-hal",
@@ -278,7 +278,7 @@ dependencies = [
 [[package]]
 name = "libconfig"
 version = "0.1.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#67dbb5932fa8ff5f143983476f741f945871d286"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
  "core_io",
  "fatfs",
@@ -289,7 +289,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#67dbb5932fa8ff5f143983476f741f945871d286"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
  "bit_field",
  "libregister",
@@ -305,7 +305,7 @@ checksum = "348108ab3fba42ec82ff6e9564fc4ca0247bdccdc68dd8af9764bbc79c3c8ffb"
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#67dbb5932fa8ff5f143983476f741f945871d286"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
  "bit_field",
  "vcell",
@@ -315,7 +315,7 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#67dbb5932fa8ff5f143983476f741f945871d286"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#c15b54f92b3d4e125ae47a0dce7abe4b2bc9e054"
 dependencies = [
  "cc",
  "compiler_builtins",

src/gateware/config.py

@@ -0,0 +1,16 @@
+from misoc.integration import cpu_interface
+
+def write_csr_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_csr_rust(
+            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
+
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+
+def write_rustc_cfg_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_rust_cfg(
+            soc.get_csr_regions(), soc.get_constants()))

src/gateware/kasli_soc.py

@@ -11,7 +11,6 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import kasli_soc
 from misoc.interconnect.csr import *
 from misoc.cores import virtual_leds
-from misoc.integration import cpu_interface
 
 from artiq.coredevice import jsondesc
 from artiq.gateware import rtio, eem_7series
@@ -27,7 +26,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 eem_iostandard_dict = {
      0: "LVDS_25",
@@ -484,31 +483,6 @@ class GenericSatellite(SoCCore):
         self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
                 for i, channel in enumerate(self.gt_drtio.channels)]
 
-
-def write_mem_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_mem_rust(
-            soc.get_memory_regions(), soc.get_memory_groups(), None))
-
-
-def write_csr_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_csr_rust(
-            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
-
-
-def write_rustc_cfg_file(soc, filename):
-    with open(filename, "w") as f:
-        for name, origin, busword, obj in soc.get_csr_regions():
-            f.write("has_{}\n".format(name.lower()))
-        for name, value in soc.get_constants():
-            if name.upper().startswith("CONFIG_"):
-                if value is None:
-                    f.write("{}\n".format(name.lower()[7:]))
-                else:
-                    f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
-
-
 def main():
     parser = argparse.ArgumentParser(
         description="ARTIQ device binary builder for generic Kasli-SoC systems")

src/gateware/zc706.py

@@ -10,7 +10,6 @@ from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
 from misoc.interconnect.csr import *
-from misoc.integration import cpu_interface
 from misoc.cores import gpio
 
 from artiq.gateware import rtio, nist_clock, nist_qc2
@@ -26,7 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
     def __init__(self, platform):
@@ -127,7 +126,6 @@ def prepare_zc706_platform(platform):
 class ZC706(SoCCore):
     def __init__(self, acpki=False):
         self.acpki = acpki
-        self.rustc_cfg = dict()
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
@@ -154,9 +152,9 @@ class ZC706(SoCCore):
                 p_CLKSWING_CFG=3),
             Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
         ]
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["si5324_as_synthesizer"] = None
-        self.rustc_cfg["si5324_soft_reset"] = None
+        self.config["HAS_SI5324"] = None
+        self.config["SI5324_AS_SYNTHESIZER"] = None
+        self.config["SI5324_SOFT_RESET"] = None
         
         self.submodules.bootstrap = CLK200BootstrapClock(platform)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf)
@@ -170,14 +168,14 @@ class ZC706(SoCCore):
         self.csr_devices.append("rtio_core")
 
         if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
+            self.config["KI_IMPL"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.rustc_cfg["ki_impl"] = "csr"
+            self.config["KI_IMPL"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -200,7 +198,6 @@ class ZC706(SoCCore):
 class _MasterBase(SoCCore):
     def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
-        self.rustc_cfg = dict()
 
         clk_freq = 100e6 if drtio100mhz else 125e6
 
@@ -271,18 +268,18 @@ class _MasterBase(SoCCore):
             memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
             self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.rustc_cfg["has_drtio"] = None
-        self.rustc_cfg["has_drtio_routing"] = None
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtio", drtio_csr_group)
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.rustc_cfg["rtio_frequency"] = str(self.gt_drtio.rtio_clk_freq/1e6)
+        self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6)
 
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
         self.csr_devices.append("si5324_rst_n")
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["si5324_as_synthesizer"] = None
+        self.config["HAS_SI5324"] = None
+        self.config["SI5324_AS_SYNTHESIZER"] = None
 
         # Constrain TX & RX timing for the first transceiver channel
         # (First channel acts as master for phase alignment for all channels' TX)
@@ -302,14 +299,14 @@ class _MasterBase(SoCCore):
         self.csr_devices.append("rtio_core")
 
         if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
+            self.config["KI_IMPL"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.rustc_cfg["ki_impl"] = "csr"
+            self.config["KI_IMPL"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -336,7 +333,6 @@ class _MasterBase(SoCCore):
 class _SatelliteBase(SoCCore):
     def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
-        self.rustc_cfg = dict()
 
         clk_freq = 100e6 if drtio100mhz else 125e6
 
@@ -425,13 +421,13 @@ class _SatelliteBase(SoCCore):
             # and registered in PS interface
             # manually, because software refers to rx/tx by halves of entire memory block, not names
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.rustc_cfg["has_drtio"] = None
-        self.rustc_cfg["has_drtio_routing"] = None
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_csr_group("drtiorep", drtiorep_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.rustc_cfg["rtio_frequency"] = str(self.gt_drtio.rtio_clk_freq/1e6)
+        self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6)
 
         # Si5324 Phaser
         self.submodules.siphaser = SiPhaser7Series(
@@ -444,8 +440,7 @@ class _SatelliteBase(SoCCore):
         self.csr_devices.append("siphaser")
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
         self.csr_devices.append("si5324_rst_n")
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["has_siphaser"] = None
+        self.config["HAS_SI5324"] = None
 
         rtio_clk_period = 1e9/self.gt_drtio.rtio_clk_freq
         # Constrain TX & RX timing for the first transceiver channel
@@ -465,14 +460,14 @@ class _SatelliteBase(SoCCore):
         self.csr_devices.append("rtio_moninj")
 
         if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
+            self.config["KI_IMPL"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.rustc_cfg["ki_impl"] = "csr"
+            self.config["KI_IMPL"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -676,27 +671,6 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
                                                   NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
 
-
-def write_csr_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_csr_rust(
-            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
-
-def write_mem_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_mem_rust(
-            soc.get_memory_regions(), soc.get_memory_groups(), None))
-
-
-def write_rustc_cfg_file(soc, filename):
-    with open(filename, "w") as f:
-        for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
-            if v is None:
-                f.write("{}\n".format(k))
-            else:
-                f.write("{}=\"{}\"\n".format(k, v))
-
-
 def main():
     parser = argparse.ArgumentParser(
         description="ARTIQ port to the ZC706 Zynq development kit")

src/runtime/src/main.rs

@@ -12,6 +12,7 @@
 #[macro_use]
 extern crate alloc;
 
+#[cfg(feature = "target_kasli_soc")]
 use core::cell::RefCell;
 
 use libasync::{block_async, task};
@@ -143,6 +144,7 @@ pub fn main_core0() {
     info!("gateware ident: {}", identifier_read(&mut [0; 64]));
 
     i2c::init();
+    #[cfg(feature = "target_kasli_soc")]
     let i2c_bus = unsafe { (i2c::I2C_BUS).as_mut().unwrap() };
 
     #[cfg(feature = "target_kasli_soc")]

src/runtime/src/rtio_acp.rs

@@ -11,6 +11,7 @@ pub const RTIO_O_STATUS_UNDERFLOW: i32 = 2;
 pub const RTIO_O_STATUS_DESTINATION_UNREACHABLE: i32 = 4;
 pub const RTIO_I_STATUS_WAIT_EVENT: i32 = 1;
 pub const RTIO_I_STATUS_OVERFLOW: i32 = 2;
+#[allow(unused)]
 pub const RTIO_I_STATUS_WAIT_STATUS: i32 = 4; // TODO
 pub const RTIO_I_STATUS_DESTINATION_UNREACHABLE: i32 = 8;
 

src/runtime/src/rtio_mgt.rs

@@ -44,6 +44,23 @@ pub mod drtio {
         unsafe { (csr::DRTIO[linkno].rx_up_read)() == 1 }
     }
 
+    async fn process_async_packets(packet: Packet) -> Option<Packet> {
+        // returns None if an async packet has been consumed
+        match packet {
+            Packet::DmaPlaybackStatus {
+                id,
+                destination,
+                error,
+                channel,
+                timestamp,
+            } => {
+                remote_dma::playback_done(id, destination, error, channel, timestamp).await;
+                None
+            }
+            other => Some(other),
+        }
+    }
+
     async fn recv_aux_timeout(linkno: u8, timeout: u64, timer: GlobalTimer) -> Result<Packet, &'static str> {
         if !link_rx_up(linkno).await {
             return Err("link went down");
@@ -66,22 +83,7 @@ pub mod drtio {
         }
         let _lock = aux_mutex.async_lock().await;
         drtioaux_async::send(linkno, request).await.unwrap();
-        loop {
-            let reply = recv_aux_timeout(linkno, 200, timer).await;
-            match reply {
-                Ok(Packet::DmaPlaybackStatus {
-                    id,
-                    destination,
-                    error,
-                    channel,
-                    timestamp,
-                }) => {
-                    remote_dma::playback_done(id, destination, error, channel, timestamp).await;
-                }
-                Ok(packet) => return Ok(packet),
-                Err(e) => return Err(e),
-            }
-        }
+        Ok(recv_aux_timeout(linkno, 200, timer).await?)
     }
 
     async fn drain_buffer(linkno: u8, draining_time: Milliseconds, timer: GlobalTimer) {
@@ -190,14 +192,11 @@ pub mod drtio {
     async fn process_unsolicited_aux(aux_mutex: &Rc<Mutex<bool>>, linkno: u8) {
         let _lock = aux_mutex.async_lock().await;
         match drtioaux_async::recv(linkno).await {
-            Ok(Some(Packet::DmaPlaybackStatus {
-                id,
-                destination,
-                error,
-                channel,
-                timestamp,
-            })) => remote_dma::playback_done(id, destination, error, channel, timestamp).await,
-            Ok(Some(packet)) => warn!("[LINK#{}] unsolicited aux packet: {:?}", linkno, packet),
+            Ok(Some(packet)) => {
+                if let Some(packet) = process_async_packets(packet).await {
+                    warn!("[LINK#{}] unsolicited aux packet: {:?}", linkno, packet);
+                }
+            }
             Ok(None) => (),
             Err(_) => warn!("[LINK#{}] aux packet error", linkno),
         }
@@ -266,51 +265,65 @@ pub mod drtio {
                 let linkno = hop - 1;
                 if destination_up(up_destinations, destination).await {
                     if up_links[linkno as usize] {
-                        let reply = aux_transact(
-                            aux_mutex,
-                            linkno,
-                            &Packet::DestinationStatusRequest {
-                                destination: destination,
-                            },
-                            timer,
-                        )
-                        .await;
-                        match reply {
-                            Ok(Packet::DestinationDownReply) => {
-                                destination_set_up(routing_table, up_destinations, destination, false).await;
-                                remote_dma::destination_changed(aux_mutex, routing_table, timer, destination, false)
+                        loop {
+                            let reply = aux_transact(
+                                aux_mutex,
+                                linkno,
+                                &Packet::DestinationStatusRequest {
+                                    destination: destination,
+                                },
+                                timer,
+                            )
+                            .await;
+                            match reply {
+                                Ok(Packet::DestinationDownReply) => {
+                                    destination_set_up(routing_table, up_destinations, destination, false).await;
+                                    remote_dma::destination_changed(
+                                        aux_mutex,
+                                        routing_table,
+                                        timer,
+                                        destination,
+                                        false,
+                                    )
                                     .await;
+                                }
+                                Ok(Packet::DestinationOkReply) => (),
+                                Ok(Packet::DestinationSequenceErrorReply { channel }) => {
+                                    error!(
+                                        "[DEST#{}] RTIO sequence error involving channel 0x{:04x}:{}",
+                                        destination,
+                                        channel,
+                                        resolve_channel_name(channel as u32)
+                                    );
+                                    unsafe { SEEN_ASYNC_ERRORS |= ASYNC_ERROR_SEQUENCE_ERROR };
+                                }
+                                Ok(Packet::DestinationCollisionReply { channel }) => {
+                                    error!(
+                                        "[DEST#{}] RTIO collision involving channel 0x{:04x}:{}",
+                                        destination,
+                                        channel,
+                                        resolve_channel_name(channel as u32)
+                                    );
+                                    unsafe { SEEN_ASYNC_ERRORS |= ASYNC_ERROR_COLLISION };
+                                }
+                                Ok(Packet::DestinationBusyReply { channel }) => {
+                                    error!(
+                                        "[DEST#{}] RTIO busy error involving channel 0x{:04x}:{}",
+                                        destination,
+                                        channel,
+                                        resolve_channel_name(channel as u32)
+                                    );
+                                    unsafe { SEEN_ASYNC_ERRORS |= ASYNC_ERROR_BUSY };
+                                }
+                                Ok(packet) => match process_async_packets(packet).await {
+                                    Some(packet) => {
+                                        error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet)
+                                    }
+                                    None => continue,
+                                },
+                                Err(e) => error!("[DEST#{}] communication failed ({})", destination, e),
                             }
-                            Ok(Packet::DestinationOkReply) => (),
-                            Ok(Packet::DestinationSequenceErrorReply { channel }) => {
-                                error!(
-                                    "[DEST#{}] RTIO sequence error involving channel 0x{:04x}:{}",
-                                    destination,
-                                    channel,
-                                    resolve_channel_name(channel as u32)
-                                );
-                                unsafe { SEEN_ASYNC_ERRORS |= ASYNC_ERROR_SEQUENCE_ERROR };
-                            }
-                            Ok(Packet::DestinationCollisionReply { channel }) => {
-                                error!(
-                                    "[DEST#{}] RTIO collision involving channel 0x{:04x}:{}",
-                                    destination,
-                                    channel,
-                                    resolve_channel_name(channel as u32)
-                                );
-                                unsafe { SEEN_ASYNC_ERRORS |= ASYNC_ERROR_COLLISION };
-                            }
-                            Ok(Packet::DestinationBusyReply { channel }) => {
-                                error!(
-                                    "[DEST#{}] RTIO busy error involving channel 0x{:04x}:{}",
-                                    destination,
-                                    channel,
-                                    resolve_channel_name(channel as u32)
-                                );
-                                unsafe { SEEN_ASYNC_ERRORS |= ASYNC_ERROR_BUSY };
-                            }
-                            Ok(packet) => error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet),
-                            Err(e) => error!("[DEST#{}] communication failed ({})", destination, e),
+                            break;
                         }
                     } else {
                         destination_set_up(routing_table, up_destinations, destination, false).await;

src/satman/src/main.rs

@@ -125,33 +125,50 @@ fn process_aux_packet(
             let hop = 0;
 
             if hop == 0 {
-                let errors;
-                unsafe {
-                    errors = csr::drtiosat::rtio_error_read();
-                }
-                if errors & 1 != 0 {
-                    let channel;
-                    unsafe {
-                        channel = csr::drtiosat::sequence_error_channel_read();
-                        csr::drtiosat::rtio_error_write(1);
-                    }
-                    drtioaux::send(0, &drtioaux::Packet::DestinationSequenceErrorReply { channel })?;
-                } else if errors & 2 != 0 {
-                    let channel;
-                    unsafe {
-                        channel = csr::drtiosat::collision_channel_read();
-                        csr::drtiosat::rtio_error_write(2);
-                    }
-                    drtioaux::send(0, &drtioaux::Packet::DestinationCollisionReply { channel })?;
-                } else if errors & 4 != 0 {
-                    let channel;
-                    unsafe {
-                        channel = csr::drtiosat::busy_channel_read();
-                        csr::drtiosat::rtio_error_write(4);
-                    }
-                    drtioaux::send(0, &drtioaux::Packet::DestinationBusyReply { channel })?;
+                if let Some(status) = dma_manager.check_state() {
+                    info!(
+                        "playback done, error: {}, channel: {}, timestamp: {}",
+                        status.error, status.channel, status.timestamp
+                    );
+                    drtioaux::send(
+                        0,
+                        &drtioaux::Packet::DmaPlaybackStatus {
+                            destination: _destination,
+                            id: status.id,
+                            error: status.error,
+                            channel: status.channel,
+                            timestamp: status.timestamp,
+                        },
+                    )?;
                 } else {
-                    drtioaux::send(0, &drtioaux::Packet::DestinationOkReply)?;
+                    let errors;
+                    unsafe {
+                        errors = csr::drtiosat::rtio_error_read();
+                    }
+                    if errors & 1 != 0 {
+                        let channel;
+                        unsafe {
+                            channel = csr::drtiosat::sequence_error_channel_read();
+                            csr::drtiosat::rtio_error_write(1);
+                        }
+                        drtioaux::send(0, &drtioaux::Packet::DestinationSequenceErrorReply { channel })?;
+                    } else if errors & 2 != 0 {
+                        let channel;
+                        unsafe {
+                            channel = csr::drtiosat::collision_channel_read();
+                            csr::drtiosat::rtio_error_write(2);
+                        }
+                        drtioaux::send(0, &drtioaux::Packet::DestinationCollisionReply { channel })?;
+                    } else if errors & 4 != 0 {
+                        let channel;
+                        unsafe {
+                            channel = csr::drtiosat::busy_channel_read();
+                            csr::drtiosat::rtio_error_write(4);
+                        }
+                        drtioaux::send(0, &drtioaux::Packet::DestinationBusyReply { channel })?;
+                    } else {
+                        drtioaux::send(0, &drtioaux::Packet::DestinationOkReply)?;
+                    }
                 }
             }
 
@@ -739,24 +756,6 @@ pub extern "C" fn main_core0() -> i32 {
                     error!("aux packet error: {:?}", e);
                 }
             }
-            if let Some(status) = dma_manager.check_state() {
-                info!(
-                    "playback done, error: {}, channel: {}, timestamp: {}",
-                    status.error, status.channel, status.timestamp
-                );
-                if let Err(e) = drtioaux::send(
-                    0,
-                    &drtioaux::Packet::DmaPlaybackStatus {
-                        destination: rank,
-                        id: status.id,
-                        error: status.error,
-                        channel: status.channel,
-                        timestamp: status.timestamp,
-                    },
-                ) {
-                    error!("error sending DMA playback status: {:?}", e);
-                }
-            }
         }
 
         drtiosat_reset_phy(true);