forked from M-Labs/artiq-zynq
enabled L2 cache and optimized ethernet
This commit is contained in:
parent
2faf74f708
commit
e592efb2b8
@ -5,6 +5,7 @@ let
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rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
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artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
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vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
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xbuild = (import ./xbuild.nix );
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in
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pkgs.stdenv.mkDerivation {
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name = "artiq-zynq-env";
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@ -15,7 +16,7 @@ in
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pkgs.llvmPackages_9.llvm
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pkgs.llvmPackages_9.clang-unwrapped
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pkgs.cacert
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pkgs.cargo-xbuild
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xbuild
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pkgs.openocd
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pkgs.openssh pkgs.rsync
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17
src/Cargo.lock
generated
17
src/Cargo.lock
generated
@ -50,8 +50,10 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
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[[package]]
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name = "compiler_builtins"
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version = "0.1.32"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "7bc4ac2c824d2bfc612cba57708198547e9a26943af0632aff033e0693074d5c"
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source = "git+https://git.m-labs.hk/pca006132/compiler-builtins-zynq.git#6dd42338c6731941614cdf979280fdffd96d532e"
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dependencies = [
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"cc",
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]
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[[package]]
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name = "core_io"
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@ -201,7 +203,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -213,7 +215,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -237,10 +239,11 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
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dependencies = [
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"bit_field",
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"libregister",
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"volatile-register",
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]
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[[package]]
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@ -252,7 +255,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
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dependencies = [
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"bit_field",
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"vcell",
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@ -262,7 +265,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -13,8 +13,16 @@ members = [
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panic = "abort"
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debug = true
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codegen-units = 1
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opt-level = 'z'
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opt-level = 's'
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lto = true
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[profile.release.package.smoltcp]
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opt-level = 2
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[profile.release.package.libasync]
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opt-level = 2
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[profile.release.package.libboard_zynq]
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opt-level = 2
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[patch.crates-io]
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core_io = { path = "./libcoreio" }
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compiler_builtins = { git = "https://git.m-labs.hk/pca006132/compiler-builtins-zynq.git"}
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@ -86,7 +86,7 @@ static CACHE_STORE: Mutex<BTreeMap<String, Vec<i32>>> = Mutex::new(BTreeMap::new
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static DMA_RECORD_STORE: Mutex<BTreeMap<String, (Vec<u8>, i64)>> = Mutex::new(BTreeMap::new());
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async fn write_header(stream: &TcpStream, reply: Reply) -> Result<()> {
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stream.send([0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()].iter().copied()).await?;
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stream.send_slice(&[0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()]).await?;
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Ok(())
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}
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@ -138,7 +138,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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let stream = stream.unwrap();
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write_header(stream, Reply::RPCRequest).await?;
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write_bool(stream, is_async).await?;
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stream.send(data.iter().copied()).await?;
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stream.send_slice(&data).await?;
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if !is_async {
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let host_request = read_request(stream, false).await?.unwrap();
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match host_request {
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@ -298,7 +298,7 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
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match request {
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Request::SystemInfo => {
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write_header(stream, Reply::SystemInfo).await?;
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stream.send("ARZQ".bytes()).await?;
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stream.send_slice("ARZQ".as_bytes()).await?;
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},
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Request::LoadKernel => {
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let buffer = read_bytes(stream, 1024*1024).await?;
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@ -320,10 +320,10 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
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info!("network addresses: {}", net_addresses);
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let eth = zynq::eth::Eth::eth0(net_addresses.hardware_addr.0.clone());
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const RX_LEN: usize = 8;
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const RX_LEN: usize = 64;
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// Number of transmission buffers (minimum is two because with
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// one, duplicate packet transmission occurs)
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const TX_LEN: usize = 8;
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const TX_LEN: usize = 64;
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let eth = eth.start_rx(RX_LEN);
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let mut eth = eth.start_tx(TX_LEN);
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@ -377,7 +377,7 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
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let connection = Rc::new(Semaphore::new(1, 1));
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let terminate = Rc::new(Semaphore::new(0, 1));
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loop {
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let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap();
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let stream = TcpStream::accept(1381, 0x10_000, 0x10_000).await.unwrap();
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if connection.try_wait().is_none() {
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// there is an existing connection
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@ -120,26 +120,26 @@ pub async fn read_chunk(stream: &TcpStream, destination: &mut [u8]) -> Result<()
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}
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pub async fn write_i8(stream: &TcpStream, value: i8) -> Result<()> {
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stream.send([value as u8].iter().copied()).await?;
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stream.send_slice(&[value as u8]).await?;
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Ok(())
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}
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pub async fn write_bool(stream: &TcpStream, value: bool) -> Result<()> {
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stream.send([value as u8].iter().copied()).await?;
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stream.send_slice(&[value as u8]).await?;
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Ok(())
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}
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pub async fn write_i32(stream: &TcpStream, value: i32) -> Result<()> {
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stream.send([
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stream.send_slice(&[
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(value >> 24) as u8,
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(value >> 16) as u8,
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(value >> 8) as u8,
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value as u8].iter().copied()).await?;
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value as u8]).await?;
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Ok(())
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}
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pub async fn write_i64(stream: &TcpStream, value: i64) -> Result<()> {
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stream.send([
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stream.send_slice(&[
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(value >> 56) as u8,
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(value >> 48) as u8,
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(value >> 40) as u8,
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@ -147,12 +147,12 @@ pub async fn write_i64(stream: &TcpStream, value: i64) -> Result<()> {
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(value >> 24) as u8,
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(value >> 16) as u8,
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(value >> 8) as u8,
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value as u8].iter().copied()).await?;
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value as u8]).await?;
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Ok(())
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}
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pub async fn write_chunk(stream: &TcpStream, value: &[u8]) -> Result<()> {
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write_i32(stream, value.len() as i32).await?;
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stream.send(value.iter().copied()).await?;
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stream.send_slice(value).await?;
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Ok(())
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}
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@ -43,7 +43,7 @@ SECTIONS
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.stack1 (NOLOAD) : ALIGN(8)
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{
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__stack1_end = .;
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. += 0x4000;
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. += 0x100;
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__stack1_start = .;
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} > OCM3
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@ -10,7 +10,8 @@ use cstr_core::CStr;
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use libcortex_a9::{
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enable_fpu,
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cache::{dcci_slice, iciallu, bpiall},
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l2c::enable_l2_cache,
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cache::{dcciall, iciallu, bpiall},
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asm::{dsb, isb},
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};
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use libboard_zynq::{
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@ -46,6 +47,7 @@ fn panic(_: &core::panic::PanicInfo) -> ! {
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#[no_mangle]
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pub fn main_core0() {
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GlobalTimer::start();
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enable_fpu();
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logger::init().unwrap();
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log::set_max_level(log::LevelFilter::Debug);
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println!(r#"
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@ -59,8 +61,8 @@ pub fn main_core0() {
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(C) 2020 M-Labs
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"#);
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info!("Simple Zynq Loader starting...");
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enable_l2_cache();
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enable_fpu();
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debug!("FPU enabled on Core0");
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const CPU_FREQ: u32 = 800_000_000;
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@ -79,12 +81,9 @@ pub fn main_core0() {
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if result < 0 {
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error!("decompression failed");
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} else {
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// Flush data cache entries for all of DDR, including
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// Flush data cache entries for all of L1 cache, including
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// Memory/Instruction Synchronization Barriers
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dcci_slice(unsafe {
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core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
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});
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dsb();
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dcciall();
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iciallu();
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bpiall();
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dsb();
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26
xbuild.nix
Normal file
26
xbuild.nix
Normal file
@ -0,0 +1,26 @@
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let
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pkgs = import <nixpkgs> {};
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in
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with pkgs;
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pkgs.rustPlatform.buildRustPackage rec {
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pname = "cargo-xbuild";
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version = "0.5.21";
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src = fetchFromGitHub {
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owner = "rust-osdev";
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repo = pname;
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rev = "v${version}";
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sha256 = "08mpnj3l6bcm1jg22lw1gcs0lkm4320fwl4p5y1s44w64963kzf7";
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};
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patches = [./xbuild.patch];
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cargoSha256 = "1pj4x8y5vfpnn8vhxqqm3vicn29870r3jh0b17q3riq4vz1a2afp";
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meta = with stdenv.lib; {
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description = "Automatically cross-compiles the sysroot crates core, compiler_builtins, and alloc";
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homepage = "https://github.com/rust-osdev/cargo-xbuild";
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license = with licenses; [ mit asl20 ];
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maintainers = with maintainers; [ johntitor xrelkd ];
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};
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}
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13
xbuild.patch
Normal file
13
xbuild.patch
Normal file
@ -0,0 +1,13 @@
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diff --git a/src/sysroot.rs b/src/sysroot.rs
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index 1f3c8d1..e5615ee 100644
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--- a/src/sysroot.rs
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+++ b/src/sysroot.rs
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@@ -163,7 +163,7 @@ version = "0.0.0"
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edition = "2018"
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[dependencies.compiler_builtins]
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-version = "0.1.0"
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+git = "https://git.m-labs.hk/pca006132/compiler-builtins-zynq.git"
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"#;
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let mut stoml = TOML.to_owned();
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