forked from M-Labs/artiq-zynq
fix analyzer target for masters
This commit is contained in:
parent
6b9212525a
commit
d51f86672a
@ -311,7 +311,7 @@ class GenericMaster(SoCCore):
|
||||
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
||||
self.csr_devices.append("routing_table")
|
||||
|
||||
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
|
||||
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
|
||||
self.ps7.s_axi_hp1)
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
@ -320,7 +320,7 @@ class _MasterBase(SoCCore):
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
|
||||
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
|
||||
self.ps7.s_axi_hp1)
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user