ident CSR demo

runtime/src/main.rs

@@ -5,15 +5,31 @@ extern crate alloc;
 
 use libboard_zynq::println;
 use libsupport_zynq::ram;
+use core::{cmp, str};
+
+mod pl;
+
+fn identifier_read(buf: &mut [u8]) -> &str {
+    unsafe {
+        pl::csr::identifier::address_write(0);
+        let len = pl::csr::identifier::data_read();
+        let len = cmp::min(len, buf.len() as u8);
+        for i in 0..len {
+            pl::csr::identifier::address_write(1 + i);
+            buf[i as usize] = pl::csr::identifier::data_read();
+        }
+        str::from_utf8_unchecked(&buf[..len as usize])
+    }
+}
 
 #[no_mangle]
 pub fn main_core0() {
-    println!("hello world 000");
+    println!("[CORE0] hello world {}", identifier_read(&mut [0; 64]));
     loop {}
 }
 
 #[no_mangle]
 pub fn main_core1() {
-    println!("hello world 111");
+    println!("[CORE1] hello world {}", identifier_read(&mut [0; 64]));
     loop {}
 }

zc706.py

@@ -1,6 +1,7 @@
 #!/usr/bin/env python
 
 import argparse
+import os
 
 from migen import *
 
@@ -18,7 +19,7 @@ class ZC706(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        SoCCore.__init__(self, platform=platform)
+        SoCCore.__init__(self, platform=platform, ident="RTIO_ZC706")
 
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
@@ -67,7 +68,7 @@ def main():
         if action == "gateware":
             soc.build()
         elif action == "rustif":
-            write_csr_file(soc, "pl.rs")
+            write_csr_file(soc, os.path.join("runtime", "src", "pl.rs"))
         else:
             raise ValueError("invalid action", action)