forked from M-Labs/artiq-zynq
satellites: add rtio_dma, connect as cri master
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4c87487fe1
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4b1ce1a6ff
@ -427,7 +427,7 @@ class GenericSatellite(SoCCore):
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.drtiosat.cri, self.rtio_dma.cri],
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[self.local_io.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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@ -476,9 +476,12 @@ class _SatelliteBase(SoCCore):
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.drtiosat.cri, self.rtio_dma.cri],
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[self.local_io.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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