From 4a2d9dc59723f2e127fecec55b84660c8fe62301 Mon Sep 17 00:00:00 2001 From: linuswck Date: Tue, 7 Nov 2023 15:40:50 +0800 Subject: [PATCH] zynq_clocking: Allow ext signal to set cur_clk csr - for example, current_clock csr can be connected to tx_init.done --- src/gateware/zynq_clocking.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index 553a43fa..5a7e7c36 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -65,7 +65,7 @@ class ClockSwitchFSM(Module): class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, ext_async_rst=None): + def __init__(self, platform, ps7, main_clk, clk_sw=None, clk_sw_status=None, freq=125e6, ext_async_rst=None, ): # assumes bootstrap clock is same freq as main and sys output self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -148,4 +148,7 @@ class SYSCRG(Module, AutoCSR): ) self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) - self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw) + if clk_sw_status is None: + self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw) + else: + self.comb += self.current_clock.status.eq(clk_sw_status)