forked from M-Labs/artiq-zynq
turn on bitstream compression
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parent
64ac021a36
commit
356860e8dc
3
zc706.py
3
zc706.py
@ -15,6 +15,9 @@ from artiq.gateware.rtio.phy import ttl_simple
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class ZC706(SoCCore):
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class ZC706(SoCCore):
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def __init__(self):
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def __init__(self):
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platform = zc706.Platform()
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platform = zc706.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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SoCCore.__init__(self, platform=platform)
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SoCCore.__init__(self, platform=platform)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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