forked from M-Labs/artiq-zynq
enable FPU on Core1
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parent
7216e9c4be
commit
1f23a1b86c
@ -128,6 +128,19 @@ fn resolve(required: &[u8]) -> Option<u32> {
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pub fn main_core1() {
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pub fn main_core1() {
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debug!("Core1 started");
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debug!("Core1 started");
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unsafe {
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llvm_asm!("
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mrc p15, 0, r1, c1, c0, 2
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orr r1, r1, (0b1111<<20)
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mcr p15, 0, r1, c1, c0, 2
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vmrs r1, fpexc
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orr r1, r1, (1<<30)
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vmsr fpexc, r1
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":::"r1");
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}
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debug!("FPU enabled on Core1");
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let mut core1_tx = None;
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let mut core1_tx = None;
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while core1_tx.is_none() {
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while core1_tx.is_none() {
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core1_tx = CHANNEL_1TO0.lock().take();
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core1_tx = CHANNEL_1TO0.lock().take();
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@ -1,6 +1,7 @@
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#![no_std]
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#![no_std]
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#![no_main]
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#![no_main]
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#![recursion_limit="1024"] // for futures_util::select!
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#![recursion_limit="1024"] // for futures_util::select!
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#![feature(llvm_asm)]
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extern crate alloc;
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extern crate alloc;
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