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zc706: si5324 is not needed for standalone target

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Sebastien Bourdeauducq 2021-08-04 09:14:19 +08:00
parent e3d3cb2311
commit 18e05c91e1
1 changed files with 0 additions and 5 deletions
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src/gateware/zc706.py
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@ -11,7 +11,6 @@ from migen_axi.integration.soc_core import SoCCore
from migen_axi.platforms import zc706 from migen_axi.platforms import zc706
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from misoc.integration import cpu_interface from misoc.integration import cpu_interface
from misoc.cores import gpio
from artiq.gateware import rtio, nist_clock, nist_qc2 from artiq.gateware import rtio, nist_clock, nist_qc2
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
@ -82,10 +81,6 @@ class ZC706(SoCCore):
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
self.rustc_cfg["HAS_SI5324"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
self.rustc_cfg["has_rtio_crg_clock_sel"] = None self.rustc_cfg["has_rtio_crg_clock_sel"] = None