586fd2f17e
Gateware: remove redundant si549.py & wrpll.py
2024-05-30 15:27:16 +08:00
377f8779a0
kasli soc: refactor to use wrpll from artiq
2024-05-30 15:25:33 +08:00
2b2ebb5354
aux: increase max payload size
2024-05-20 15:20:06 +08:00
35ea0ed2ca
WRPLL: add filter for DRTIO 100MHz
2024-05-08 18:50:55 +08:00
cdf4ff24c0
WRPLL: replace PI controller with new filter
2024-05-08 18:50:55 +08:00
285b02c4b1
WRPLL: remove anti-windup
2024-05-08 18:50:55 +08:00
53cb592d19
kasli soc: add rtio_frequency cfg for runtime
2024-05-08 16:14:56 +08:00
1d603c73b7
DDMTD: replace 1st edge to median edge deglitcher
2024-04-29 13:05:02 +08:00
61315c29b9
Si549: recalibrate TAG_OFFSET for ISERDESE2
2024-04-29 13:03:30 +08:00
3f57de6ec7
DDMTD: replace FD with ISERDESE2
2024-04-29 13:03:30 +08:00
cca23aa2a5
wrpll runtime: reduce mmcm output jitter
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rtio_clocking: update mmcm setting to use HIGH bandwidth
2024-04-29 11:20:50 +08:00
2bbaea3ad5
SMAFreqMulti: set mmcm bw to HIGH for lower jitter
2024-04-29 11:20:50 +08:00
0a19f8fb89
satman: revert async flag changes
2024-04-26 11:37:14 +08:00
a30c7d1f3a
runtime: drtio aux refactoring, revert async flag
2024-04-26 11:37:14 +08:00
2d10503c20
libboard_artiq: support multiple aux rx buffers
2024-04-24 17:12:57 +08:00
92a29051f7
drtio_aux_controller: support aux_buffer_count
2024-04-24 17:12:39 +08:00
14fa038118
Firmware: Runtime WRPLL
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runtime: drive CLK_SEL to true when si549 is used
runtime & libboard_artiq: allow standalone to use io_expander
si549: add bit bang mmcm dynamic configuration
si549: add frequency counter for refclk
rtio_clocking & si549: add 125Mhz wrpll refclk setup
2024-04-12 16:38:46 +08:00
b81323af30
Firmware: Satman skew calibration & tester
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cargo template: add calibrate_wrpll_skew feature
tag collector: add TAG_OFFSET for Satman WRPLL
tag collector: add TAG_OFFSET getter & setter for calibration
wrpll: add skew tester and calibration
wrpll: gate calibration behind calibrate_wrpll_skew feature
2024-04-12 16:38:46 +08:00
291777f764
Firmware: Satman WRPLL
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satman: drive CLK_SEL to true when si549 is used
satman : add main & helper si549 setup
satman : add WRPLL select_recovered_clock
si549: add tag collector to process gtx & main tags
si549: add frequency counter to set BASE_ADPLL
si549: add set_adpll for main & helper PLL
si549: add main & helper PLL
FIQ & si549: replace dummy with a custom handler for gtx & main tags ISR
2024-04-12 16:38:39 +08:00
a1d80fb93b
Firmware: Si549 and io_expander
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io_expander: set CLK_SEL pin to output when si549 is used
io_expander: gate virtual leds for standalone
si549: add bit bang i2c
si549: add si549 programming
si549: add main & helper setup
2024-04-11 15:18:10 +08:00
7827c7b803
Gateware: kasli_soc WRPLL setup
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kasli_soc: use enable_wrpll from json to switch from si5324 to si549
kasli_soc: add wrpll for all variants
kasli_soc: add gtx & main tag nFIQ for all variants
kasli_soc: add clk_synth_se for master & satellite
kasli_soc: add wrpll_refclk for runtime
kasli_soc: add skewtester for satman
kasli_soc: add WRPLL_REF_CLK config for firmware
2024-04-11 15:18:10 +08:00
e4d8d44c7c
Gateware: WRPLL
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ddmtd: add DDMTD and deglitcher
wrpll: add helper clockdomain
wrpll: add frequency counter
wrpll: add skewtester
wrpll: add gtx & main tag collection
wrpll: add gtx & main tag eventmanager for shared peripheral interrupt
wrpll: add SMA frequency multiplier to generate 125Mhz refclk
si549: add i2c and adpll programmer
2024-04-11 15:18:04 +08:00
4455f740d2
main: set exception vector table addr
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linker: add exceptions start & end symbol
2024-03-07 15:37:42 +08:00
63bf1c81d4
fiq: use dummy handler to fix compilation error
2024-03-07 13:26:52 +08:00
bfb582f99b
cargo fmt
2024-02-01 14:43:41 +08:00
52e64fb2f9
subkernel: use negative ID for argument passing
2024-02-01 14:43:41 +08:00
facc98058c
subkernel: fix DMA return control to wrong master
2024-02-01 14:43:41 +08:00
f0f81dbf8a
subkernel: support no-timeout, message passing
2024-02-01 14:43:41 +08:00
30e6bf4a3a
subkernel: add support for (d)dma
2024-01-11 12:33:02 +08:00
8f4e30dd9c
satman: support sub-subkernels, routing
2024-01-11 12:33:02 +08:00
e31a31c4ff
master: drtioaux:
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- support async flag
- source in packets
- rerouting packets
2024-01-11 12:33:02 +08:00
6ca1719033
comms: fix compilation on standalone
2023-11-14 14:08:31 +08:00
aebc739c1e
add support for tar flashable (sub)kernels
2023-11-13 11:24:23 +08:00
e1b2c45813
kasli_soc & zc706: Fix GTX Clock Path during INIT
2023-11-07 18:55:08 +08:00
e6372b9766
zynq_clocking: Allow ext signal to set cur_clk csr
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- for example, current_clock csr can be connected to tx_init.done
2023-11-07 18:55:08 +08:00
07044752b6
zynq_clocking: add ext_async_rst to AsyncRstSYNCR
2023-11-07 18:55:08 +08:00
79fc5a7789
zynq_clocking: expose mmcm_locked for SYSCRG
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- mmcm_locked -> self.mmcm_locked
2023-11-07 18:55:08 +08:00
6c8346ca5f
subkernel: improve stability,
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fix exception on awaiting message
2023-11-02 16:58:34 +08:00
b76f634686
drtio: increase robustness for longer payloads
2023-11-02 14:48:52 +08:00
4a34777b97
refactor i2c, io_expander, task under the same cfg
2023-10-25 11:52:04 +08:00
43e4527392
fix kasli-soc demo compilation warning
2023-10-25 11:45:13 +08:00
0a3bfc9a61
subkernel: separate tags and data
2023-10-18 12:03:43 +08:00
d3fbfd75b0
Fix grabber build and warning
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-10-18 11:24:43 +08:00
b768d5648c
Add grabber module
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-10-16 14:35:20 +08:00
812aea33b3
rustfmt
2023-10-11 17:56:30 +08:00
136e24f597
kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1
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- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
2023-10-11 16:45:26 +08:00
a4d1be00c0
Firmware: Add drtio_eem.rs support
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- Port from Artiq repo
- Initialize the drtio_eem on main, rtio_clocking
- Driver for eem_transceiver
2023-10-10 11:22:05 +08:00
b15322b6ba
kasli_soc: Add support for shuttler on gateware
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- Port from artiq repo
- Add EEM_DRTIO gateware
2023-10-10 11:22:05 +08:00
8fd1306145
zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
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- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
2023-10-10 11:21:34 +08:00
a28a819b18
add manifests target to PHONY
2023-10-09 18:29:53 +08:00
