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03d9827a5a
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acpki: working
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2020-09-09 21:24:49 +08:00 |
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537f4968eb
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acpki: add legacy i_status/o_status registers
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2020-08-04 17:31:35 +08:00 |
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62988a580e
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acpki: update for combined RTIO channel/address
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2020-08-04 17:28:15 +08:00 |
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1e20259c36
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fix acpki selection
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2020-08-04 13:26:45 +08:00 |
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f8d4036451
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add ACP kernel initiator
Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
M-Labs/artiq-zynq#55
Work-in-progress, only gateware part and build system, untested.
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2020-08-04 13:15:26 +08:00 |
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59cf2764ce
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dma: report AXI bus error
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2020-07-21 12:47:20 +08:00 |
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21135c6a41
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analyzer: report AXI bus errors
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2020-07-20 19:51:22 +08:00 |
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523524c319
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zc706: add RTIO log channels
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2020-07-19 14:05:35 +08:00 |
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f69e41af5e
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gateware: fix VADJ I/O standard conflict
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2020-07-16 17:58:31 +08:00 |
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6a361893c2
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gateware: make LEDs common to all variants
Makes quick testing easier.
|
2020-07-16 17:36:27 +08:00 |
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ae7ca22db9
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dma: fix endianness issues
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2020-07-16 17:27:08 +08:00 |
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10a12245a3
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analyzer: fix endianness issue
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2020-07-16 17:10:09 +08:00 |
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0c6db0d12c
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analyzer: use 32-bit byte_count
|
2020-07-16 11:36:04 +08:00 |
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0b0ca8de49
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analyzer: drive wid and wstrb
|
2020-07-15 23:11:19 +08:00 |
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8e758ecc17
|
add RTIO analyzer core (untested)
|
2020-07-15 23:06:34 +08:00 |
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b68cb137e5
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dma: style
|
2020-07-15 23:06:14 +08:00 |
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12ba867268
|
dma: fix and cleanup test
|
2020-07-13 18:58:08 +08:00 |
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5c3c3c26b5
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dma: fix inflight_cnt and eop generation
|
2020-07-13 18:51:55 +08:00 |
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ea96cf96d3
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dma: add simulation test (WIP)
|
2020-07-13 12:04:10 +08:00 |
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10888cc6c6
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dma: remove unneeded import
|
2020-07-13 10:42:02 +08:00 |
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a7073edf79
|
add DMA core (untested)
|
2020-07-13 10:37:17 +08:00 |
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e3ff21b1b5
|
create gateware folder
|
2020-07-11 17:49:54 +08:00 |
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