From dce37a52aa4488aeb3e91f8975ab3a21da6e84d0 Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Mon, 20 Feb 2023 13:06:31 +0800
Subject: [PATCH] KasliSoC satellite: fix serdes timing

---
 src/gateware/kasli_soc.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index d33e4e96..06102528 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -342,6 +342,8 @@ class GenericSatellite(SoCCore):
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.crg.cd_sys = self.sys_crg.cd_sys
 
+        fix_serdes_timing_path(platform)
+
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
         if has_grabber: