forked from M-Labs/artiq-zynq
remove redpitaya and coraz7 support
This commit is contained in:
parent
dcd3cbc488
commit
8d4e42be32
@ -136,11 +136,5 @@ in
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(build { target = "zc706"; variant = "acpki_simple"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
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(build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
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(build { target = "coraz7"; variant = "10"; }) //
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(build { target = "coraz7"; variant = "07s"; }) //
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(build { target = "coraz7"; variant = "acpki_10"; }) //
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(build { target = "coraz7"; variant = "acpki_07s"; }) //
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(build { target = "redpitaya"; variant = "simple"; }) //
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(build { target = "redpitaya"; variant = "acpki_simple"; }) //
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{ inherit zynq-rs; }
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)
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@ -1,191 +0,0 @@
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#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import coraz7
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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import dma
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import analyzer
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import acpki
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self.clock_sel = CSRStorage()
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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# user_sma_clock = platform.request("user_sma_clock")
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# platform.add_period_constraint(user_sma_clock.p, 8.0)
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# self.specials += Instance("IBUFDS",
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# i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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# o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self.clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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class CoraZ7(SoCCore):
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def __init__(self, device_variant="10", acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = coraz7.Platform(device_variant=device_variant)
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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class Simple(CoraZ7):
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def __init__(self, **kwargs):
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CoraZ7.__init__(self, **kwargs)
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platform = self.platform
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rtio_channels = []
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for i in range(2):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the Cora Z7 Zynq development kit")
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parser.add_argument("-r", default=None,
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help="build Rust interface into the specified file")
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parser.add_argument("-c", default=None,
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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parser.add_argument("-V", "--variant", default="10",
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help="variant: "
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"[acpki_]10/07s "
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"(default: %(default)s)")
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args = parser.parse_args()
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variant = args.variant.lower()
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acpki = variant.startswith("acpki_")
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if acpki:
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variant = variant[6:]
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try:
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soc = Simple(device_variant=variant, acpki=acpki)
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc.finalize()
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if args.r is not None:
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write_csr_file(soc, args.r)
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if args.c is not None:
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write_rustc_cfg_file(soc, args.c)
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if args.g is not None:
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soc.build(build_dir=args.g)
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if __name__ == "__main__":
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main()
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@ -1,191 +0,0 @@
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#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import redpitaya
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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import dma
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import analyzer
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import acpki
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self.clock_sel = CSRStorage()
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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# user_sma_clock = platform.request("user_sma_clock")
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# platform.add_period_constraint(user_sma_clock.p, 8.0)
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# self.specials += Instance("IBUFDS",
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# i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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# o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self.clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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class Redpitaya(SoCCore):
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def __init__(self, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = redpitaya.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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class Simple(Redpitaya):
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def __init__(self, **kwargs):
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Redpitaya.__init__(self, **kwargs)
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platform = self.platform
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rtio_channels = []
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for i in range(2):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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VARIANTS = {cls.__name__.lower(): cls for cls in [Simple]}
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the Redpitaya Zynq development kit")
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parser.add_argument("-r", default=None,
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help="build Rust interface into the specified file")
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parser.add_argument("-c", default=None,
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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parser.add_argument("-V", "--variant", default="10",
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help="variant: "
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"[acpki_]simple "
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"(default: %(default)s)")
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args = parser.parse_args()
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variant = args.variant.lower()
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acpki = variant.startswith("acpki_")
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if acpki:
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variant = variant[6:]
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soc = Simple(acpki=acpki)
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soc.finalize()
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if args.r is not None:
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write_csr_file(soc, args.r)
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if args.c is not None:
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write_rustc_cfg_file(soc, args.c)
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if args.g is not None:
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soc.build(build_dir=args.g)
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if __name__ == "__main__":
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main()
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@ -7,8 +7,6 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
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default = ["target_zc706"]
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