From 7aec419ed6cb03d8d51d42b6c1aaf249514e1d50 Mon Sep 17 00:00:00 2001 From: pca006132 Date: Fri, 10 Jul 2020 17:17:52 +0800 Subject: [PATCH] kernel: added core1 instruction cache flush --- src/runtime/src/kernel/core1.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/runtime/src/kernel/core1.rs b/src/runtime/src/kernel/core1.rs index e0a97d02..cd633795 100644 --- a/src/runtime/src/kernel/core1.rs +++ b/src/runtime/src/kernel/core1.rs @@ -5,7 +5,7 @@ use alloc::borrow::ToOwned; use log::{debug, info, error}; use cslice::CSlice; -use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel}; +use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel}; use dyld::{self, Library}; use crate::eh_artiq; use super::{ @@ -92,6 +92,7 @@ impl KernelImage { // Flush data cache entries for the image in DDR, including // Memory/Instruction Synchronization Barriers dcci_slice(self.library.image.data); + iciallu(); (mem::transmute::(self.__modinit__))();