forked from M-Labs/artiq-zynq
dma: fix inflight_cnt and eop generation
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@ -42,13 +42,20 @@ class AXIReader(Module):
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# UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands"
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# UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands"
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inflight_cnt = Signal(max=128)
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inflight_cnt = Signal(max=128)
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self.sync += inflight_cnt.eq(inflight_cnt + (ar.valid & ar.ready) - (r.valid & r.ready))
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request_done = Signal()
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reply_done = Signal()
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self.comb += [
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request_done.eq(ar.valid & ar.ready),
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reply_done.eq(r.valid & r.ready & r.last)
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]
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self.sync += inflight_cnt.eq(inflight_cnt + request_done - reply_done)
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self.comb += [
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self.comb += [
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self.source.stb.eq(r.valid),
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self.source.stb.eq(r.valid),
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r.ready.eq(self.source.ack),
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r.ready.eq(self.source.ack),
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self.source.data.eq(r.data),
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self.source.data.eq(r.data),
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self.source.eop.eq(eop_pending & r.last & (inflight_cnt == 0))
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# Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
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self.source.eop.eq(eop_pending & r.last & (inflight_cnt == 1))
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]
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]
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@ -45,7 +45,7 @@ class AXIMemorySim:
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raise ValueError
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raise ValueError
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addr = request.addr//self.align + i
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addr = request.addr//self.align + i
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if addr < len(self.queue):
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if addr < len(self.queue):
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data = self.queue[addr]
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data = self.data[addr]
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else:
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else:
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data = 0
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data = 0
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yield from self.bus.write_r(request.id, data, last=i == request_len-1)
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yield from self.bus.write_r(request.id, data, last=i == request_len-1)
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