From 3cf86a63359699d9f74f65d0913a19792c6f0d26 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 12 Apr 2022 13:44:53 +0800 Subject: [PATCH] satellites: add rtio_crg cfg --- src/gateware/kasli_soc.py | 1 + src/gateware/zc706.py | 1 + src/satman/src/main.rs | 9 ++++++--- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 694f50f6..04579367 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -340,6 +340,7 @@ class GenericSatellite(SoCCore): self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq) self.csr_devices.append("rtio_crg") + self.rustc_cfg["has_rtio_crg"] = None data_pads = [platform.request("sfp", i) for i in range(4)] diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index de61bb4f..edd9d2a3 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -431,6 +431,7 @@ class _SatelliteBase(SoCCore): self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) self.csr_devices.append("rtio_crg") + self.rustc_cfg["has_rtio_crg"] = None fix_serdes_timing_path(self.platform) def add_rtio(self, rtio_channels): diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index 2282616e..9544f011 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -392,7 +392,7 @@ fn drtiosat_process_errors() { #[cfg(has_rtio_crg)] -fn init_rtio_crg(timer: GlobalTimer) { +fn init_rtio_crg(timer: &mut GlobalTimer) { unsafe { csr::rtio_crg::pll_reset_write(0); } @@ -401,10 +401,13 @@ fn init_rtio_crg(timer: GlobalTimer) { if !locked { error!("RTIO clock failed"); } + else { + info!("RTIO PLL locked"); + } } #[cfg(not(has_rtio_crg))] -fn init_rtio_crg(_timer: GlobalTimer) { } +fn init_rtio_crg(_timer: &mut GlobalTimer) { } fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) { let now = timer.get_time(); @@ -477,7 +480,7 @@ pub extern fn main_core0() -> i32 { unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); } - init_rtio_crg(timer); + init_rtio_crg(&mut timer); #[cfg(has_drtio_routing)] let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];