117 lines
4.5 KiB
Rust
117 lines
4.5 KiB
Rust
///! System timer used for RTIC scheduling
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///!
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///! # Design
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///! The SystemTimer is an RTIC monotonic timer that can be used for scheduling tasks in RTIC.
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///! This timer is used in place of the cycle counter to allow the timer to tick at a slower rate
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///! than the CPU clock. This allows for longer scheduling periods with less resolution. This is
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///! needed for infrequent (e.g. multiple second) telemetry periods.
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///!
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///! # Limitations
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///! This implementation relies on sufficient timer polling to not miss timer counter overflows. If
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///! the timer is not polled often enough, it's possible that an overflow would be missed and time
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///! would "halt" for a shore period of time. This could be fixed in the future by instead
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///! listening for the overflow interrupt instead of polling the overflow state.
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use hal::prelude::*;
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use stm32h7xx_hal as hal;
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// A global buffer indicating how many times the internal counter has overflowed.
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static mut OVERFLOWS: u32 = 0;
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/// System timer used for implementing RTIC scheduling.
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///
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/// # Note
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/// The system timer must be initialized before being used.
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pub struct SystemTimer {}
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impl SystemTimer {
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/// Initialize the system timer.
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///
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/// # Args
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/// * `timer` - The hardware timer used for implementing the RTIC monotonic.
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pub fn initialize(mut timer: hal::timer::Timer<hal::device::TIM15>) {
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timer.pause();
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// Have the system timer operate at a tick rate of 10KHz (100uS per tick). With this
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// configuration and a 65535 period, we get an overflow once every 6.5 seconds.
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timer.set_tick_freq(10.khz());
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timer.apply_freq();
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timer.resume();
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}
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/// Convert a provided number of seconds into timer ticks.
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pub fn ticks_from_secs(secs: u32) -> i32 {
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(secs * 10_000) as i32
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}
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}
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impl rtic::Monotonic for SystemTimer {
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/// Instants are stored in 32-bit signed integers. With a 10KHz tick rate, this means an
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/// instant can store up to ~59 hours of time before overflowing.
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type Instant = i32;
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/// The ratio of the CPU clock to the system timer.
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fn ratio() -> rtic::Fraction {
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rtic::Fraction {
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// At 10KHz with a 400MHz CPU clock, the CPU clock runs 40,000 times faster than
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// the system timer.
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numerator: 40_000,
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denominator: 1,
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}
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}
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/// Get the current time instant.
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///
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/// # Note
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/// The time will overflow into -59 hours after the first 59 hours. This time value is intended
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/// for use in calculating time delta, and should not be used for timestamping purposes due to
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/// roll-over.
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fn now() -> i32 {
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// Note(unsafe): Multiple interrupt contexts have access to the underlying timer, so care
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// is taken when reading and modifying register values.
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let regs = unsafe { &*hal::device::TIM15::ptr() };
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cortex_m::interrupt::free(|_cs| {
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loop {
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// Checking for overflows of the current counter must be performed atomically. Any
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// other task that is accessing the current time could potentially race for the
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// registers. Note that this is only required for writing to global state (e.g. timer
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// registers and overflow counter)
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// Check for overflows and clear the overflow bit atomically. This must be done in
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// a critical section to prevent race conditions on the status register.
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if regs.sr.read().uif().bit_is_set() {
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regs.sr.modify(|_, w| w.uif().clear_bit());
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unsafe {
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OVERFLOWS += 1;
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}
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}
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let current_value = regs.cnt.read().bits();
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// Check that an overflow didn't occur since we just cleared the overflow bit. If
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// it did, loop around and retry.
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if regs.sr.read().uif().bit_is_clear() {
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// Note(unsafe): We are in a critical section, so it is safe to read the
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// global variable.
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return unsafe {
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((OVERFLOWS << 16) + current_value) as i32
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};
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}
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}
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})
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}
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/// Reset the timer count.
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unsafe fn reset() {
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// Note: The timer must be safely configured in `SystemTimer::initialize()`.
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let regs = &*hal::device::TIM15::ptr();
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OVERFLOWS = 0;
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regs.cnt.reset();
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}
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/// Get a timestamp correlating to zero time.
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fn zero() -> i32 {
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0
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}
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}
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