53 lines
2.3 KiB
Rust
53 lines
2.3 KiB
Rust
use stm32h7xx_hal::time::MegaHertz;
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/// The ADC setup time is the number of seconds after the CSn line goes low before the serial clock
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/// may begin. This is used for performing the internal ADC conversion.
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pub const ADC_SETUP_TIME: f32 = 220e-9;
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/// The maximum DAC/ADC serial clock line frequency. This is a hardware limit.
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pub const ADC_DAC_SCK_MAX: MegaHertz = MegaHertz(50);
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/// The optimal counting frequency of the hardware timers used for timestamping and sampling.
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pub const TIMER_FREQUENCY: MegaHertz = MegaHertz(100);
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/// The QSPI frequency for communicating with the pounder DDS.
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pub const POUNDER_QSPI_FREQUENCY: MegaHertz = MegaHertz(40);
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/// The delay after initiating a QSPI transfer before asserting the IO_Update for the pounder DDS.
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// Pounder Profile writes are always 16 bytes, with 2 cycles required per byte, coming out to a
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// total of 32 QSPI clock cycles. The QSPI is configured for 40MHz, so this comes out to an offset
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// of 800nS. We use 900ns to be safe.
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pub const POUNDER_IO_UPDATE_DELAY: f32 = 900e-9;
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/// The duration to assert IO_Update for the pounder DDS.
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// IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile write. With pounder
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// SYNC_CLK running at 100MHz (1/4 of the pounder reference clock of 500MHz), this corresponds to
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// 32ns. To accomodate rounding errors, we use 50ns instead.
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pub const POUNDER_IO_UPDATE_DURATION: f32 = 50e-9;
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/// The DDS reference clock frequency in MHz.
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pub const DDS_REF_CLK: MegaHertz = MegaHertz(100);
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/// The multiplier used for the DDS reference clock PLL.
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pub const DDS_MULTIPLIER: u8 = 5;
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/// The DDS system clock frequency after the internal PLL multiplication.
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#[allow(dead_code)]
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pub const DDS_SYSTEM_CLK: MegaHertz =
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MegaHertz(DDS_REF_CLK.0 * DDS_MULTIPLIER as u32);
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/// The divider from the DDS system clock to the SYNC_CLK output (sync-clk is always 1/4 of sysclk).
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#[allow(dead_code)]
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pub const DDS_SYNC_CLK_DIV: u8 = 4;
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// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
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// equal to 10ns per tick.
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pub const ADC_SAMPLE_TICKS: u16 =
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1 << crate::configuration::ADC_SAMPLE_TICKS_LOG2;
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// The desired ADC sample processing buffer size.
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pub const SAMPLE_BUFFER_SIZE: usize =
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1 << crate::configuration::SAMPLE_BUFFER_SIZE_LOG2;
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pub type SampleBuffer = [u16; SAMPLE_BUFFER_SIZE];
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