1269 lines
46 KiB
Rust
1269 lines
46 KiB
Rust
#![deny(warnings)]
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#![allow(clippy::missing_safety_doc)]
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#![no_std]
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#![no_main]
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#![cfg_attr(feature = "nightly", feature(asm))]
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// Enable returning `!`
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#![cfg_attr(feature = "nightly", feature(never_type))]
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#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
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#[inline(never)]
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#[panic_handler]
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#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() };
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gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
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#[cfg(feature = "nightly")]
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core::intrinsics::abort();
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#[cfg(not(feature = "nightly"))]
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unsafe {
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core::intrinsics::abort();
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}
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}
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#[cfg(feature = "semihosting")]
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extern crate panic_semihosting;
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#[cfg(not(any(feature = "nightly", feature = "semihosting")))]
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extern crate panic_halt;
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#[macro_use]
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extern crate log;
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#[allow(unused_imports)]
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use core::convert::TryInto;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use cortex_m_rt::exception;
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use rtic::cyccnt::{Instant, U32Ext};
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::prelude::*;
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use hal::{
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dma::{
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config::Priority,
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dma::{DMAReq, DmaConfig},
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traits::TargetAddress,
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MemoryToPeripheral, PeripheralToMemory, Transfer,
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},
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ethernet::{self, PHY},
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};
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use smoltcp as net;
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use smoltcp::iface::Routes;
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use smoltcp::wire::Ipv4Address;
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use heapless::{consts::*, String};
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// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
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// equal to 10ns per tick.
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// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
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const ADC_SAMPLE_TICKS_LOG2: u16 = 8;
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const ADC_SAMPLE_TICKS: u16 = 1 << ADC_SAMPLE_TICKS_LOG2;
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// The desired ADC sample processing buffer size.
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const SAMPLE_BUFFER_SIZE_LOG2: usize = 3;
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const SAMPLE_BUFFER_SIZE: usize = 1 << SAMPLE_BUFFER_SIZE_LOG2;
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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const IIR_CASCADE_LENGTH: usize = 1;
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// Frequency scaling factor for lock-in harmonic demodulation.
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const HARMONIC: u32 = 1;
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// Phase offset applied to the lock-in demodulation signal.
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const PHASE_OFFSET: u32 = 0;
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#[link_section = ".sram3.eth"]
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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mod adc;
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mod afe;
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mod dac;
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mod design_parameters;
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mod digital_input_stamper;
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mod eeprom;
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mod hrtimer;
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mod pounder;
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mod server;
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mod timers;
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use adc::{Adc0Input, Adc1Input};
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use dac::{Dac0Output, Dac1Output};
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use dsp::{
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iir, iir_int,
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reciprocal_pll::TimestampHandler,
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trig::{atan2, cossin},
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Complex,
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};
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use pounder::DdsOutput;
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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#[cfg(feature = "semihosting")]
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fn init_log() {
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use cortex_m_log::log::{init as init_log, Logger};
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use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
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use log::LevelFilter;
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static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
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let logger = Logger {
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inner: InterruptOk::<_>::stdout().unwrap(),
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level: LevelFilter::Info,
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};
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let logger = unsafe { LOGGER.get_or_insert(logger) };
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init_log(logger).unwrap();
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}
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// Pull in build information (from `built` crate)
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mod build_info {
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#![allow(dead_code)]
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// include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
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pub struct NetStorage {
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ip_addrs: [net::wire::IpCidr; 1],
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neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8],
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routes_storage: [Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 1],
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}
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static mut NET_STORE: NetStorage = NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [net::wire::IpCidr::Ipv6(
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net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
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)],
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neighbor_cache: [None; 8],
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routes_storage: [None; 1],
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};
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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type AFE0 = afe::ProgrammableGainAmplifier<
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hal::gpio::gpiof::PF2<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiof::PF5<hal::gpio::Output<hal::gpio::PushPull>>,
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>;
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type AFE1 = afe::ProgrammableGainAmplifier<
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hal::gpio::gpiod::PD14<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiod::PD15<hal::gpio::Output<hal::gpio::PushPull>>,
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>;
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macro_rules! route_request {
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($request:ident,
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readable_attributes: [$($read_attribute:tt: $getter:tt),*],
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modifiable_attributes: [$($write_attribute:tt: $TYPE:ty, $setter:tt),*]) => {
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match $request.req {
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server::AccessRequest::Read => {
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match $request.attribute {
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$(
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$read_attribute => {
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#[allow(clippy::redundant_closure_call)]
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let value = match $getter() {
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Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to read attribute"),
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};
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let encoded_data: String<U256> = match serde_json_core::to_string(&value) {
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Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to encode attribute value"),
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};
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server::Response::success($request.attribute, &encoded_data)
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},
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)*
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_ => server::Response::error($request.attribute, "Unknown attribute")
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}
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},
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server::AccessRequest::Write => {
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match $request.attribute {
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$(
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$write_attribute => {
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let new_value = match serde_json_core::from_str::<$TYPE>(&$request.value) {
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Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to decode value"),
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};
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#[allow(clippy::redundant_closure_call)]
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match $setter(new_value) {
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Ok(_) => server::Response::success($request.attribute, &$request.value),
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Err(_) => server::Response::error($request.attribute,
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"Failed to set attribute"),
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}
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}
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)*
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_ => server::Response::error($request.attribute, "Unknown attribute")
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}
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}
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}
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}
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}
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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input_stamper: digital_input_stamper::InputStamper,
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timestamp_handler: TimestampHandler,
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iir_lockin: iir_int::IIR,
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iir_state_lockin: [iir_int::IIRState; 2],
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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dds_output: Option<DdsOutput>,
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// Note: It appears that rustfmt generates a format that GDB cannot recognize, which
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// results in GDB breakpoints being set improperly.
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#[rustfmt::skip]
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net_interface: net::iface::EthernetInterface<
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'static,
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'static,
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'static,
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ethernet::EthernetDMA<'static>>,
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eth_mac: ethernet::phy::LAN8742A<ethernet::EthernetMAC>,
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mac_addr: net::wire::EthernetAddress,
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pounder: Option<pounder::PounderDevices>,
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pounder_stamper: Option<pounder::timestamp::Timestamper>,
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// Format: iir_state[ch][cascade-no][coeff]
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#[init([[[0.; 5]; IIR_CASCADE_LENGTH]; 2])]
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iir_state: [[iir::IIRState; IIR_CASCADE_LENGTH]; 2],
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#[init([[iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; IIR_CASCADE_LENGTH]; 2])]
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iir_ch: [[iir::IIR; IIR_CASCADE_LENGTH]; 2],
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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let dp = c.device;
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let mut cp = c.core;
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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// Enable SRAM3 for the ethernet descriptor ring.
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dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Clear reset flags.
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dp.RCC.rsr.write(|w| w.rmvf().set_bit());
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// Select the PLLs for SPI.
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dp.RCC
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.d2ccip1r
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.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &dp.SYSCFG);
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init_log();
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let mut delay = hal::delay::Delay::new(cp.SYST, ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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let mut gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
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let afe0 = {
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let a0_pin = gpiof.pf2.into_push_pull_output();
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let a1_pin = gpiof.pf5.into_push_pull_output();
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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let afe1 = {
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let a0_pin = gpiod.pd14.into_push_pull_output();
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let a1_pin = gpiod.pd15.into_push_pull_output();
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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let dma_streams =
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hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1);
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// Configure timer 2 to trigger conversions for the ADC
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let mut sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer2 =
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dp.TIM2.timer(1.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer2.pause();
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timer2.reset_counter();
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timer2.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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let mut sampling_timer = timers::SamplingTimer::new(timer2);
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sampling_timer.set_period_ticks((ADC_SAMPLE_TICKS - 1) as u32);
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// The sampling timer is used as the master timer for the shadow-sampling timer. Thus,
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// it generates a trigger whenever it is enabled.
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sampling_timer
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};
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let mut shadow_sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer3 =
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dp.TIM3.timer(1.khz(), ccdr.peripheral.TIM3, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer3.pause();
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timer3.reset_counter();
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timer3.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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let mut shadow_sampling_timer =
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timers::ShadowSamplingTimer::new(timer3);
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shadow_sampling_timer.set_period_ticks(ADC_SAMPLE_TICKS - 1);
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// The shadow sampling timer is a slave-mode timer to the sampling timer. It should
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// always be in-sync - thus, we configure it to operate in slave mode using "Trigger
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// mode".
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// For TIM3, TIM2 can be made the internal trigger connection using ITR1. Thus, the
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// SamplingTimer start now gates the start of the ShadowSamplingTimer.
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shadow_sampling_timer.set_slave_mode(
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timers::TriggerSource::Trigger1,
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timers::SlaveMode::Trigger,
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);
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shadow_sampling_timer
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};
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let sampling_timer_channels = sampling_timer.channels();
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let shadow_sampling_timer_channels = shadow_sampling_timer.channels();
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let mut timestamp_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer5 =
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dp.TIM5.timer(1.khz(), ccdr.peripheral.TIM5, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer5.pause();
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timer5.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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// The timestamp timer must run at exactly a multiple of the sample timer based on the
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// batch size. To accomodate this, we manually set the prescaler identical to the sample
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// timer, but use a period that is longer.
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let mut timer = timers::TimestampTimer::new(timer5);
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let period =
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digital_input_stamper::calculate_timestamp_timer_period();
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timer.set_period_ticks(period);
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timer
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};
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let timestamp_timer_channels = timestamp_timer.channels();
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// Configure the SPI interfaces to the ADCs and DACs.
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let adcs = {
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let adc0 = {
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let spi_miso = gpiob
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.pb14
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiob
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.pb10
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiob
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.pb9
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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|
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.communication_mode(hal::spi::CommunicationMode::Receiver)
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.cs_delay(design_parameters::ADC_SETUP_TIME);
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|
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
|
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config,
|
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design_parameters::ADC_DAC_SCK_MAX,
|
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ccdr.peripheral.SPI2,
|
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&ccdr.clocks,
|
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);
|
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|
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Adc0Input::new(
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spi,
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dma_streams.0,
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dma_streams.1,
|
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dma_streams.2,
|
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sampling_timer_channels.ch1,
|
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shadow_sampling_timer_channels.ch1,
|
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)
|
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};
|
|
|
|
let adc1 = {
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|
let spi_miso = gpiob
|
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.pb4
|
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.into_alternate_af6()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpioc
|
|
.pc10
|
|
.into_alternate_af6()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _spi_nss = gpioa
|
|
.pa15
|
|
.into_alternate_af6()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
})
|
|
.manage_cs()
|
|
.suspend_when_inactive()
|
|
.communication_mode(hal::spi::CommunicationMode::Receiver)
|
|
.cs_delay(design_parameters::ADC_SETUP_TIME);
|
|
|
|
let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
config,
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
ccdr.peripheral.SPI3,
|
|
&ccdr.clocks,
|
|
);
|
|
|
|
Adc1Input::new(
|
|
spi,
|
|
dma_streams.3,
|
|
dma_streams.4,
|
|
dma_streams.5,
|
|
sampling_timer_channels.ch2,
|
|
shadow_sampling_timer_channels.ch2,
|
|
)
|
|
};
|
|
|
|
(adc0, adc1)
|
|
};
|
|
|
|
let dacs = {
|
|
let _dac_clr_n =
|
|
gpioe.pe12.into_push_pull_output().set_high().unwrap();
|
|
let _dac0_ldac_n =
|
|
gpioe.pe11.into_push_pull_output().set_low().unwrap();
|
|
let _dac1_ldac_n =
|
|
gpioe.pe15.into_push_pull_output().set_low().unwrap();
|
|
|
|
let dac0_spi = {
|
|
let spi_miso = gpioe
|
|
.pe5
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpioe
|
|
.pe2
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _spi_nss = gpioe
|
|
.pe4
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
})
|
|
.manage_cs()
|
|
.suspend_when_inactive()
|
|
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
|
.swap_mosi_miso();
|
|
|
|
dp.SPI4.spi(
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
config,
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
ccdr.peripheral.SPI4,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let dac1_spi = {
|
|
let spi_miso = gpiof
|
|
.pf8
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpiof
|
|
.pf7
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _spi_nss = gpiof
|
|
.pf6
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
})
|
|
.manage_cs()
|
|
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
|
.suspend_when_inactive()
|
|
.swap_mosi_miso();
|
|
|
|
dp.SPI5.spi(
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
config,
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
ccdr.peripheral.SPI5,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let dac0 = Dac0Output::new(
|
|
dac0_spi,
|
|
dma_streams.6,
|
|
sampling_timer_channels.ch3,
|
|
);
|
|
let dac1 = Dac1Output::new(
|
|
dac1_spi,
|
|
dma_streams.7,
|
|
sampling_timer_channels.ch4,
|
|
);
|
|
(dac0, dac1)
|
|
};
|
|
|
|
let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
|
|
let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
|
|
let mut fp_led_2 = gpiog.pg4.into_push_pull_output();
|
|
let mut fp_led_3 = gpiod.pd12.into_push_pull_output();
|
|
|
|
fp_led_0.set_low().unwrap();
|
|
fp_led_1.set_low().unwrap();
|
|
fp_led_2.set_low().unwrap();
|
|
fp_led_3.set_low().unwrap();
|
|
|
|
// Measure the Pounder PGOOD output to detect if pounder is present on Stabilizer.
|
|
let pounder_pgood = gpiob.pb13.into_pull_down_input();
|
|
delay.delay_ms(2u8);
|
|
let (pounder_devices, dds_output) = if pounder_pgood.is_high().unwrap()
|
|
{
|
|
let ad9959 = {
|
|
let qspi_interface = {
|
|
// Instantiate the QUADSPI pins and peripheral interface.
|
|
let qspi_pins = {
|
|
let _qspi_ncs = gpioc
|
|
.pc11
|
|
.into_alternate_af9()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let clk = gpiob
|
|
.pb2
|
|
.into_alternate_af9()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io0 = gpioe
|
|
.pe7
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io1 = gpioe
|
|
.pe8
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io2 = gpioe
|
|
.pe9
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io3 = gpioe
|
|
.pe10
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
(clk, io0, io1, io2, io3)
|
|
};
|
|
|
|
let qspi = hal::qspi::Qspi::bank2(
|
|
dp.QUADSPI,
|
|
qspi_pins,
|
|
design_parameters::POUNDER_QSPI_FREQUENCY,
|
|
&ccdr.clocks,
|
|
ccdr.peripheral.QSPI,
|
|
);
|
|
|
|
pounder::QspiInterface::new(qspi).unwrap()
|
|
};
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
let reset_pin = gpiog.pg6.into_push_pull_output();
|
|
#[cfg(not(feature = "pounder_v1_1"))]
|
|
let reset_pin = gpioa.pa0.into_push_pull_output();
|
|
|
|
let mut io_update = gpiog.pg7.into_push_pull_output();
|
|
|
|
let ref_clk: hal::time::Hertz =
|
|
design_parameters::DDS_REF_CLK.into();
|
|
|
|
let ad9959 = ad9959::Ad9959::new(
|
|
qspi_interface,
|
|
reset_pin,
|
|
&mut io_update,
|
|
&mut delay,
|
|
ad9959::Mode::FourBitSerial,
|
|
ref_clk.0 as f32,
|
|
design_parameters::DDS_MULTIPLIER,
|
|
)
|
|
.unwrap();
|
|
|
|
// Return IO_Update
|
|
gpiog.pg7 = io_update.into_analog();
|
|
|
|
ad9959
|
|
};
|
|
|
|
let io_expander = {
|
|
let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
|
|
let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
|
|
let i2c1 = dp.I2C1.i2c(
|
|
(scl, sda),
|
|
100.khz(),
|
|
ccdr.peripheral.I2C1,
|
|
&ccdr.clocks,
|
|
);
|
|
mcp23017::MCP23017::default(i2c1).unwrap()
|
|
};
|
|
|
|
let spi = {
|
|
let spi_mosi = gpiod
|
|
.pd7
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_miso = gpioa
|
|
.pa6
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpiog
|
|
.pg11
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
});
|
|
|
|
// The maximum frequency of this SPI must be limited due to capacitance on the MISO
|
|
// line causing a long RC decay.
|
|
dp.SPI1.spi(
|
|
(spi_sck, spi_miso, spi_mosi),
|
|
config,
|
|
5.mhz(),
|
|
ccdr.peripheral.SPI1,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let (adc1, adc2) = {
|
|
let (mut adc1, mut adc2) = hal::adc::adc12(
|
|
dp.ADC1,
|
|
dp.ADC2,
|
|
&mut delay,
|
|
ccdr.peripheral.ADC12,
|
|
&ccdr.clocks,
|
|
);
|
|
|
|
let adc1 = {
|
|
adc1.calibrate();
|
|
adc1.enable()
|
|
};
|
|
|
|
let adc2 = {
|
|
adc2.calibrate();
|
|
adc2.enable()
|
|
};
|
|
|
|
(adc1, adc2)
|
|
};
|
|
|
|
let adc1_in_p = gpiof.pf11.into_analog();
|
|
let adc2_in_p = gpiof.pf14.into_analog();
|
|
|
|
let pounder_devices = pounder::PounderDevices::new(
|
|
io_expander,
|
|
spi,
|
|
adc1,
|
|
adc2,
|
|
adc1_in_p,
|
|
adc2_in_p,
|
|
)
|
|
.unwrap();
|
|
|
|
let dds_output = {
|
|
let io_update_trigger = {
|
|
let _io_update = gpiog
|
|
.pg7
|
|
.into_alternate_af2()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
// Configure the IO_Update signal for the DDS.
|
|
let mut hrtimer = hrtimer::HighResTimerE::new(
|
|
dp.HRTIM_TIME,
|
|
dp.HRTIM_MASTER,
|
|
dp.HRTIM_COMMON,
|
|
ccdr.clocks,
|
|
ccdr.peripheral.HRTIM,
|
|
);
|
|
|
|
// IO_Update occurs after a fixed delay from the QSPI write. Note that the timer
|
|
// is triggered after the QSPI write, which can take approximately 120nS, so
|
|
// there is additional margin.
|
|
hrtimer.configure_single_shot(
|
|
hrtimer::Channel::Two,
|
|
design_parameters::POUNDER_IO_UPDATE_DURATION,
|
|
design_parameters::POUNDER_IO_UPDATE_DELAY,
|
|
);
|
|
|
|
// Ensure that we have enough time for an IO-update every sample.
|
|
let sample_frequency = {
|
|
let timer_frequency: hal::time::Hertz =
|
|
design_parameters::TIMER_FREQUENCY.into();
|
|
timer_frequency.0 as f32 / ADC_SAMPLE_TICKS as f32
|
|
};
|
|
|
|
let sample_period = 1.0 / sample_frequency;
|
|
assert!(
|
|
sample_period
|
|
> design_parameters::POUNDER_IO_UPDATE_DELAY
|
|
);
|
|
|
|
hrtimer
|
|
};
|
|
|
|
let (qspi, config) = ad9959.freeze();
|
|
DdsOutput::new(qspi, io_update_trigger, config)
|
|
};
|
|
|
|
(Some(pounder_devices), Some(dds_output))
|
|
} else {
|
|
(None, None)
|
|
};
|
|
|
|
let mut eeprom_i2c = {
|
|
let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
|
|
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
|
|
dp.I2C2.i2c(
|
|
(scl, sda),
|
|
100.khz(),
|
|
ccdr.peripheral.I2C2,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
// Configure ethernet pins.
|
|
{
|
|
// Reset the PHY before configuring pins.
|
|
let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
|
|
eth_phy_nrst.set_low().unwrap();
|
|
delay.delay_us(200u8);
|
|
eth_phy_nrst.set_high().unwrap();
|
|
let _rmii_ref_clk = gpioa
|
|
.pa1
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_mdio = gpioa
|
|
.pa2
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_mdc = gpioc
|
|
.pc1
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_crs_dv = gpioa
|
|
.pa7
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_rxd0 = gpioc
|
|
.pc4
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_rxd1 = gpioc
|
|
.pc5
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_tx_en = gpiob
|
|
.pb11
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_txd0 = gpiob
|
|
.pb12
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_txd1 = gpiog
|
|
.pg14
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
}
|
|
|
|
let mac_addr = match eeprom::read_eui48(&mut eeprom_i2c) {
|
|
Err(_) => {
|
|
info!("Could not read EEPROM, using default MAC address");
|
|
net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
|
|
}
|
|
Ok(raw_mac) => net::wire::EthernetAddress(raw_mac),
|
|
};
|
|
|
|
let (network_interface, eth_mac) = {
|
|
// Configure the ethernet controller
|
|
let (eth_dma, eth_mac) = unsafe {
|
|
ethernet::new_unchecked(
|
|
dp.ETHERNET_MAC,
|
|
dp.ETHERNET_MTL,
|
|
dp.ETHERNET_DMA,
|
|
&mut DES_RING,
|
|
mac_addr,
|
|
ccdr.peripheral.ETH1MAC,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
// Reset and initialize the ethernet phy.
|
|
let mut lan8742a =
|
|
ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0));
|
|
lan8742a.phy_reset();
|
|
lan8742a.phy_init();
|
|
|
|
unsafe { ethernet::enable_interrupt() };
|
|
|
|
let store = unsafe { &mut NET_STORE };
|
|
|
|
store.ip_addrs[0] = net::wire::IpCidr::new(
|
|
net::wire::IpAddress::v4(10, 0, 16, 99),
|
|
24,
|
|
);
|
|
|
|
let default_v4_gw = Ipv4Address::new(10, 0, 16, 1);
|
|
let mut routes = Routes::new(&mut store.routes_storage[..]);
|
|
routes.add_default_ipv4_route(default_v4_gw).unwrap();
|
|
|
|
let neighbor_cache =
|
|
net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
|
|
|
|
let interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
|
|
.ethernet_addr(mac_addr)
|
|
.neighbor_cache(neighbor_cache)
|
|
.ip_addrs(&mut store.ip_addrs[..])
|
|
.routes(routes)
|
|
.finalize();
|
|
|
|
(interface, lan8742a)
|
|
};
|
|
|
|
cp.SCB.enable_icache();
|
|
|
|
// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
|
|
// info!("Built on {}", build_info::BUILT_TIME_UTC);
|
|
// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
|
|
|
|
// Utilize the cycle counter for RTIC scheduling.
|
|
cp.DWT.enable_cycle_counter();
|
|
|
|
let mut input_stamper = {
|
|
let trigger = gpioa.pa3.into_alternate_af2();
|
|
digital_input_stamper::InputStamper::new(
|
|
trigger,
|
|
timestamp_timer_channels.ch4,
|
|
)
|
|
};
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
let pounder_stamper = {
|
|
let dma2_streams =
|
|
hal::dma::dma::StreamsTuple::new(dp.DMA2, ccdr.peripheral.DMA2);
|
|
|
|
let etr_pin = gpioa.pa0.into_alternate_af3();
|
|
|
|
// The frequency in the constructor is dont-care, as we will modify the period + clock
|
|
// source manually below.
|
|
let tim8 =
|
|
dp.TIM8.timer(1.khz(), ccdr.peripheral.TIM8, &ccdr.clocks);
|
|
let mut timestamp_timer = timers::PounderTimestampTimer::new(tim8);
|
|
|
|
// Pounder is configured to generate a 500MHz reference clock, so a 125MHz sync-clock is
|
|
// output. As a result, dividing the 125MHz sync-clk provides a 31.25MHz tick rate for
|
|
// the timestamp timer. 31.25MHz corresponds with a 32ns tick rate.
|
|
timestamp_timer.set_external_clock(timers::Prescaler::Div4);
|
|
timestamp_timer.start();
|
|
|
|
// We want the pounder timestamp timer to overflow once per batch.
|
|
let tick_ratio = {
|
|
let sync_clk_mhz: f32 = design_parameters::DDS_SYSTEM_CLK.0
|
|
as f32
|
|
/ design_parameters::DDS_SYNC_CLK_DIV as f32;
|
|
sync_clk_mhz / design_parameters::TIMER_FREQUENCY.0 as f32
|
|
};
|
|
|
|
let period = (tick_ratio
|
|
* ADC_SAMPLE_TICKS as f32
|
|
* SAMPLE_BUFFER_SIZE as f32) as u32
|
|
/ 4;
|
|
timestamp_timer.set_period_ticks((period - 1).try_into().unwrap());
|
|
let tim8_channels = timestamp_timer.channels();
|
|
|
|
let stamper = pounder::timestamp::Timestamper::new(
|
|
timestamp_timer,
|
|
dma2_streams.0,
|
|
tim8_channels.ch1,
|
|
&mut sampling_timer,
|
|
etr_pin,
|
|
);
|
|
|
|
Some(stamper)
|
|
};
|
|
|
|
#[cfg(not(feature = "pounder_v1_1"))]
|
|
let pounder_stamper = None;
|
|
|
|
let timestamp_handler = TimestampHandler::new(
|
|
4,
|
|
3,
|
|
ADC_SAMPLE_TICKS_LOG2 as usize,
|
|
SAMPLE_BUFFER_SIZE_LOG2,
|
|
);
|
|
let iir_lockin = iir_int::IIR::default();
|
|
let iir_state_lockin = [iir_int::IIRState::default(); 2];
|
|
|
|
// Start sampling ADCs.
|
|
sampling_timer.start();
|
|
timestamp_timer.start();
|
|
input_stamper.start();
|
|
|
|
init::LateResources {
|
|
afes: (afe0, afe1),
|
|
|
|
adcs,
|
|
dacs,
|
|
input_stamper,
|
|
dds_output,
|
|
pounder: pounder_devices,
|
|
pounder_stamper,
|
|
|
|
timestamp_handler,
|
|
iir_lockin,
|
|
iir_state_lockin,
|
|
|
|
eeprom_i2c,
|
|
net_interface: network_interface,
|
|
eth_mac,
|
|
mac_addr,
|
|
}
|
|
}
|
|
|
|
/// Main DSP processing routine for Stabilizer.
|
|
///
|
|
/// # Note
|
|
/// Processing time for the DSP application code is bounded by the following constraints:
|
|
///
|
|
/// DSP application code starts after the ADC has generated a batch of samples and must be
|
|
/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
|
|
/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
|
|
///
|
|
/// The DSP application code must also fill out the next DAC output buffer in time such that the
|
|
/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
|
|
/// it's possible that old DAC codes will be generated on the output and the output samples will
|
|
/// be delayed by 1 batch.
|
|
///
|
|
/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
|
|
/// the same time bounds, meeting one also means the other is also met.
|
|
#[task(binds=DMA1_STR4, resources=[pounder_stamper, adcs, dacs, iir_state, iir_ch, dds_output, input_stamper, timestamp_handler, iir_lockin, iir_state_lockin], priority=2)]
|
|
fn process(c: process::Context) {
|
|
if let Some(stamper) = c.resources.pounder_stamper {
|
|
let pounder_timestamps = stamper.acquire_buffer();
|
|
info!("{:?}", pounder_timestamps);
|
|
}
|
|
|
|
let adc_samples = [
|
|
c.resources.adcs.0.acquire_buffer(),
|
|
c.resources.adcs.1.acquire_buffer(),
|
|
];
|
|
|
|
let dac_samples = [
|
|
c.resources.dacs.0.acquire_buffer(),
|
|
c.resources.dacs.1.acquire_buffer(),
|
|
];
|
|
|
|
let iir_lockin = c.resources.iir_lockin;
|
|
let iir_state_lockin = c.resources.iir_state_lockin;
|
|
let iir_ch = c.resources.iir_ch;
|
|
let iir_state = c.resources.iir_state;
|
|
|
|
let (pll_phase, pll_frequency) = c
|
|
.resources
|
|
.timestamp_handler
|
|
.update(c.resources.input_stamper.latest_timestamp());
|
|
let frequency = pll_frequency.wrapping_mul(HARMONIC);
|
|
let mut phase =
|
|
PHASE_OFFSET.wrapping_add(pll_phase.wrapping_mul(HARMONIC));
|
|
|
|
for i in 0..adc_samples[0].len() {
|
|
let m = cossin((phase as i32).wrapping_neg());
|
|
phase = phase.wrapping_add(frequency);
|
|
|
|
let signal = Complex(
|
|
iir_lockin.update(
|
|
&mut iir_state_lockin[0],
|
|
((adc_samples[0][i] as i64 * m.0 as i64) >> 16) as _,
|
|
),
|
|
iir_lockin.update(
|
|
&mut iir_state_lockin[1],
|
|
((adc_samples[0][i] as i64 * m.1 as i64) >> 16) as _,
|
|
),
|
|
);
|
|
|
|
let mut magnitude =
|
|
(signal.0 * signal.0 + signal.1 * signal.1) as _;
|
|
let mut phase = atan2(signal.1, signal.0) as _;
|
|
|
|
for j in 0..iir_state[0].len() {
|
|
magnitude =
|
|
iir_ch[0][j].update(&mut iir_state[0][j], magnitude);
|
|
phase = iir_ch[1][j].update(&mut iir_state[1][j], phase);
|
|
}
|
|
|
|
// Note(unsafe): range clipping to i16 is ensured by IIR filters above.
|
|
unsafe {
|
|
dac_samples[0][i] =
|
|
magnitude.to_int_unchecked::<i16>() as u16 ^ 0x8000;
|
|
dac_samples[1][i] =
|
|
phase.to_int_unchecked::<i16>() as u16 ^ 0x8000;
|
|
}
|
|
}
|
|
|
|
if let Some(dds_output) = c.resources.dds_output {
|
|
let builder = dds_output.builder().update_channels(
|
|
&[pounder::Channel::Out0.into()],
|
|
Some(u32::MAX / 4),
|
|
None,
|
|
None,
|
|
);
|
|
|
|
builder.write_profile();
|
|
}
|
|
}
|
|
|
|
#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afes])]
|
|
fn idle(mut c: idle::Context) -> ! {
|
|
let mut socket_set_entries: [_; 8] = Default::default();
|
|
let mut sockets =
|
|
net::socket::SocketSet::new(&mut socket_set_entries[..]);
|
|
|
|
let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
|
|
let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
|
|
let tcp_handle = {
|
|
let tcp_rx_buffer =
|
|
net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
|
|
let tcp_tx_buffer =
|
|
net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
|
|
let tcp_socket =
|
|
net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
|
|
sockets.add(tcp_socket)
|
|
};
|
|
|
|
let mut server = server::Server::new();
|
|
|
|
let mut time = 0u32;
|
|
let mut next_ms = Instant::now();
|
|
|
|
// TODO: Replace with reference to CPU clock from CCDR.
|
|
next_ms += 400_000.cycles();
|
|
|
|
loop {
|
|
let tick = Instant::now() > next_ms;
|
|
|
|
if tick {
|
|
next_ms += 400_000.cycles();
|
|
time += 1;
|
|
}
|
|
|
|
{
|
|
let socket =
|
|
&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle);
|
|
if socket.state() == net::socket::TcpState::CloseWait {
|
|
socket.close();
|
|
} else if !(socket.is_open() || socket.is_listening()) {
|
|
socket
|
|
.listen(1235)
|
|
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
|
|
} else {
|
|
server.poll(socket, |req| {
|
|
info!("Got request: {:?}", req);
|
|
route_request!(req,
|
|
readable_attributes: [
|
|
"stabilizer/iir/state": (|| {
|
|
let state = c.resources.iir_state.lock(|iir_state|
|
|
server::Status {
|
|
t: time,
|
|
x0: iir_state[0][0][0],
|
|
y0: iir_state[0][0][2],
|
|
x1: iir_state[1][0][0],
|
|
y1: iir_state[1][0][2],
|
|
});
|
|
|
|
Ok::<server::Status, ()>(state)
|
|
}),
|
|
// "_b" means cascades 2nd IIR
|
|
"stabilizer/iir_b/state": (|| {
|
|
let state = c.resources.iir_state.lock(|iir_state|
|
|
server::Status {
|
|
t: time,
|
|
x0: iir_state[0][IIR_CASCADE_LENGTH-1][0],
|
|
y0: iir_state[0][IIR_CASCADE_LENGTH-1][2],
|
|
x1: iir_state[1][IIR_CASCADE_LENGTH-1][0],
|
|
y1: iir_state[1][IIR_CASCADE_LENGTH-1][2],
|
|
});
|
|
|
|
Ok::<server::Status, ()>(state)
|
|
}),
|
|
"stabilizer/afe0/gain": (|| c.resources.afes.0.get_gain()),
|
|
"stabilizer/afe1/gain": (|| c.resources.afes.1.get_gain())
|
|
],
|
|
|
|
modifiable_attributes: [
|
|
"stabilizer/iir0/state": server::IirRequest, (|req: server::IirRequest| {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
if req.channel > 1 {
|
|
return Err(());
|
|
}
|
|
|
|
iir_ch[req.channel as usize][0] = req.iir;
|
|
|
|
Ok::<server::IirRequest, ()>(req)
|
|
})
|
|
}),
|
|
"stabilizer/iir1/state": server::IirRequest, (|req: server::IirRequest| {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
if req.channel > 1 {
|
|
return Err(());
|
|
}
|
|
|
|
iir_ch[req.channel as usize][0] = req.iir;
|
|
|
|
Ok::<server::IirRequest, ()>(req)
|
|
})
|
|
}),
|
|
"stabilizer/iir_b0/state": server::IirRequest, (|req: server::IirRequest| {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
if req.channel > 1 {
|
|
return Err(());
|
|
}
|
|
|
|
iir_ch[req.channel as usize][IIR_CASCADE_LENGTH-1] = req.iir;
|
|
|
|
Ok::<server::IirRequest, ()>(req)
|
|
})
|
|
}),
|
|
"stabilizer/iir_b1/state": server::IirRequest,(|req: server::IirRequest| {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
if req.channel > 1 {
|
|
return Err(());
|
|
}
|
|
|
|
iir_ch[req.channel as usize][IIR_CASCADE_LENGTH-1] = req.iir;
|
|
|
|
Ok::<server::IirRequest, ()>(req)
|
|
})
|
|
}),
|
|
"stabilizer/afe0/gain": afe::Gain, (|gain| {
|
|
c.resources.afes.0.set_gain(gain);
|
|
Ok::<(), ()>(())
|
|
}),
|
|
"stabilizer/afe1/gain": afe::Gain, (|gain| {
|
|
c.resources.afes.1.set_gain(gain);
|
|
Ok::<(), ()>(())
|
|
})
|
|
]
|
|
)
|
|
});
|
|
}
|
|
}
|
|
|
|
let sleep = match c.resources.net_interface.poll(
|
|
&mut sockets,
|
|
net::time::Instant::from_millis(time as i64),
|
|
) {
|
|
Ok(changed) => !changed,
|
|
Err(net::Error::Unrecognized) => true,
|
|
Err(e) => {
|
|
info!("iface poll error: {:?}", e);
|
|
true
|
|
}
|
|
};
|
|
|
|
if sleep {
|
|
cortex_m::asm::wfi();
|
|
}
|
|
}
|
|
}
|
|
|
|
#[task(binds = ETH, priority = 1)]
|
|
fn eth(_: eth::Context) {
|
|
unsafe { ethernet::interrupt_handler() }
|
|
}
|
|
|
|
#[task(binds = SPI2, priority = 3)]
|
|
fn spi2(_: spi2::Context) {
|
|
panic!("ADC0 input overrun");
|
|
}
|
|
|
|
#[task(binds = SPI3, priority = 3)]
|
|
fn spi3(_: spi3::Context) {
|
|
panic!("ADC0 input overrun");
|
|
}
|
|
|
|
#[task(binds = SPI4, priority = 3)]
|
|
fn spi4(_: spi4::Context) {
|
|
panic!("DAC0 output error");
|
|
}
|
|
|
|
#[task(binds = SPI5, priority = 3)]
|
|
fn spi5(_: spi5::Context) {
|
|
panic!("DAC1 output error");
|
|
}
|
|
|
|
extern "C" {
|
|
// hw interrupt handlers for RTIC to use for scheduling tasks
|
|
// one per priority
|
|
fn DCMI();
|
|
fn JPEG();
|
|
fn SDMMC();
|
|
}
|
|
};
|
|
|
|
#[exception]
|
|
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
|
|
panic!("HardFault at {:#?}", ef);
|
|
}
|
|
|
|
#[exception]
|
|
fn DefaultHandler(irqn: i16) {
|
|
panic!("Unhandled exception (IRQn = {})", irqn);
|
|
}
|