513 lines
16 KiB
Rust
513 lines
16 KiB
Rust
//! # Lockin
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//!
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//! THe `lockin` application implements a lock-in amplifier using either an external or internally
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//! generated
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//!
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//! ## Features
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//! * Up to 800 kHz sampling
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//! * Up to 400 kHz modulation frequency
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//! * Supports internal and external reference sources:
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//! 1. Internal: Generate reference internally and output on one of the channel outputs
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//! 2. External: Reciprocal PLL, reference input applied to DI0.
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//! * Adjustable PLL and locking time constants
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//! * Adjustable phase offset and harmonic index
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//! * Run-time configurable output modes (in-phase, quadrature, magnitude, log2 power, phase, frequency)
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//! * Input/output data streamng via UDP
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//!
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//! ## Settings
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//! Refer to the [Settings] structure for documentation of run-time configurable settings for this
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//! application.
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//!
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//! ## Telemetry
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//! Refer to [Telemetry] for information about telemetry reported by this application.
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//!
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//! ## Livestreaming
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//! This application streams raw ADC and DAC data over UDP. Refer to
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//! [stabilizer::net::data_stream](../stabilizer/net/data_stream/index.html) for more information.
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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use core::{
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convert::TryFrom,
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sync::atomic::{fence, Ordering},
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};
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use mutex_trait::prelude::*;
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use dsp::{Accu, Complex, ComplexExt, Lockin, RPLL};
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use stabilizer::{
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hardware::{
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self,
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adc::{Adc0Input, Adc1Input, AdcCode},
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afe::Gain,
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dac::{Dac0Output, Dac1Output, DacCode},
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embedded_hal::digital::v2::InputPin,
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hal,
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input_stamper::InputStamper,
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signal_generator,
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system_timer::SystemTimer,
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DigitalInput0, DigitalInput1, AFE0, AFE1,
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},
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net::{
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data_stream::{FrameGenerator, StreamFormat, StreamTarget},
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miniconf::Miniconf,
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serde::Deserialize,
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telemetry::{Telemetry, TelemetryBuffer},
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NetworkState, NetworkUsers,
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},
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};
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// The logarithm of the number of samples in each batch process. This corresponds with 2^3 samples
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// per batch = 8 samples
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const BATCH_SIZE_SIZE_LOG2: u8 = 3;
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// The logarithm of the number of 100MHz timer ticks between each sample. This corresponds with a
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// sampling period of 2^7 = 128 ticks. At 100MHz, 10ns per tick, this corresponds to a sampling
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// period of 1.28 uS or 781.25 KHz.
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const ADC_SAMPLE_TICKS_LOG2: u8 = 7;
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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enum Conf {
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/// Output the lockin magnitude.
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Magnitude,
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/// Output the phase of the lockin
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Phase,
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/// Output the lockin reference frequency as a sinusoid
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ReferenceFrequency,
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/// Output the logarithmic power of the lockin
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LogPower,
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/// Output the in-phase component of the lockin signal.
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InPhase,
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/// Output the quadrature component of the lockin signal.
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Quadrature,
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/// Output the lockin internal modulation frequency as a sinusoid
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Modulation,
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}
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#[derive(Copy, Clone, Debug, Miniconf, Deserialize, PartialEq)]
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enum LockinMode {
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/// Utilize an internally generated reference for demodulation
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Internal,
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/// Utilize an external modulation signal supplied to DI0
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External,
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}
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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pub struct Settings {
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/// Configure the Analog Front End (AFE) gain.
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///
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/// # Path
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/// `afe/<n>`
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///
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/// * <n> specifies which channel to configure. <n> := [0, 1]
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///
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/// # Value
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/// Any of the variants of [Gain] enclosed in double quotes.
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afe: [Gain; 2],
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/// Specifies the operational mode of the lockin.
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///
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/// # Path
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/// `lockin_mode`
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///
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/// # Value
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/// One of the variants of [LockinMode] enclosed in double quotes.
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lockin_mode: LockinMode,
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/// Specifis the PLL time constant.
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///
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/// # Path
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/// `pll_tc/<n>`
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///
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/// * <n> specifies which channel to configure. <n> := [0, 1]
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///
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/// # Value
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/// The PLL time constant as an unsigned byte (0-255).
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pll_tc: [u8; 2],
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/// Specifies the lockin time constant.
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///
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/// # Path
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/// `lockin_tc`
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///
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/// # Value
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/// The lockin low-pass time constant as an unsigned byte (0-255).
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lockin_tc: u8,
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/// Specifies which harmonic to use for the lockin.
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///
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/// # Path
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/// `lockin_harmonic`
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///
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/// # Value
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/// Harmonic index of the LO. -1 to _de_modulate the fundamental (complex conjugate)
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lockin_harmonic: i32,
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/// Specifies the LO phase offset.
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///
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/// # Path
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/// `lockin_phase`
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///
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/// # Value
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/// Demodulation LO phase offset. Units are in terms of i32, where [i32::MIN] is equivalent to
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/// -pi and [i32::MAX] is equivalent to +pi.
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lockin_phase: i32,
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/// Specifies DAC output mode.
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///
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/// # Path
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/// `output_conf/<n>`
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///
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/// * <n> specifies which channel to configure. <n> := [0, 1]
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///
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/// # Value
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/// One of the variants of [Conf] enclosed in double quotes.
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output_conf: [Conf; 2],
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/// Specifies the telemetry output period in seconds.
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///
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/// # Path
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/// `telemetry_period`
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///
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/// # Value
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/// Any non-zero value less than 65536.
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telemetry_period: u16,
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/// Specifies the target for data livestreaming.
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///
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/// # Path
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/// `stream_target`
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///
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/// # Value
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/// See [StreamTarget#miniconf]
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stream_target: StreamTarget,
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}
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impl Default for Settings {
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fn default() -> Self {
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Self {
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afe: [Gain::G1; 2],
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lockin_mode: LockinMode::External,
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
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lockin_tc: 6, // lockin lowpass time constant
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lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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lockin_phase: 0, // Demodulation LO phase offset
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output_conf: [Conf::InPhase, Conf::Quadrature],
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// The default telemetry period in seconds.
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telemetry_period: 10,
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stream_target: StreamTarget::default(),
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}
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}
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}
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#[rtic::app(device = stabilizer::hardware::hal::stm32, peripherals = true, monotonic = stabilizer::hardware::system_timer::SystemTimer)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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network: NetworkUsers<Settings, Telemetry>,
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settings: Settings,
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telemetry: TelemetryBuffer,
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digital_inputs: (DigitalInput0, DigitalInput1),
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generator: FrameGenerator,
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signal_generator: signal_generator::SignalGenerator,
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timestamper: InputStamper,
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pll: RPLL,
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lockin: Lockin<4>,
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}
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#[init(spawn=[settings_update, telemetry, ethernet_link])]
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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let (mut stabilizer, _pounder) = hardware::setup::setup(
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c.core,
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c.device,
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1 << BATCH_SIZE_SIZE_LOG2,
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1 << ADC_SAMPLE_TICKS_LOG2,
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);
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let mut network = NetworkUsers::new(
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stabilizer.net.stack,
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stabilizer.net.phy,
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stabilizer.cycle_counter,
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env!("CARGO_BIN_NAME"),
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stabilizer.net.mac_address,
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option_env!("BROKER")
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.unwrap_or("10.34.16.10")
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.parse()
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.unwrap(),
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);
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let generator = network.configure_streaming(
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StreamFormat::AdcDacData,
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1u8 << BATCH_SIZE_SIZE_LOG2,
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);
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let settings = Settings::default();
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let pll = RPLL::new(ADC_SAMPLE_TICKS_LOG2 + BATCH_SIZE_SIZE_LOG2);
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// Spawn a settings and telemetry update for default settings.
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c.spawn.settings_update().unwrap();
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c.spawn.telemetry().unwrap();
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// Spawn the ethernet link servicing task.
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c.spawn.ethernet_link().unwrap();
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// Enable ADC/DAC events
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stabilizer.adcs.0.start();
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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// Start recording digital input timestamps.
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stabilizer.timestamp_timer.start();
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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// Enable the timestamper.
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stabilizer.timestamper.start();
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let signal_config = {
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let frequency_tuning_word =
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(1u64 << (32 - BATCH_SIZE_SIZE_LOG2)) as i32;
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signal_generator::Config {
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// Same frequency as batch size.
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frequency_tuning_word: [
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frequency_tuning_word,
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frequency_tuning_word,
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],
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// 1V Amplitude
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amplitude: DacCode::try_from(1.0).unwrap().into(),
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signal: signal_generator::Signal::Cosine,
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}
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};
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init::LateResources {
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afes: stabilizer.afes,
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adcs: stabilizer.adcs,
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dacs: stabilizer.dacs,
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network,
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digital_inputs: stabilizer.digital_inputs,
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timestamper: stabilizer.timestamper,
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telemetry: TelemetryBuffer::default(),
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signal_generator: signal_generator::SignalGenerator::new(
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signal_config,
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),
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settings,
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generator,
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pll,
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lockin: Lockin::default(),
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}
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}
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/// Main DSP processing routine.
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///
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/// See `dual-iir` for general notes on processing time and timing.
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///
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/// This is an implementation of a externally (DI0) referenced PLL lockin on the ADC0 signal.
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/// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
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/// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
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#[task(binds=DMA1_STR4, resources=[adcs, dacs, lockin, timestamper, pll, settings, telemetry, generator, signal_generator], priority=2)]
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#[inline(never)]
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#[link_section = ".itcm.process"]
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fn process(mut c: process::Context) {
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let process::Resources {
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adcs: (ref mut adc0, ref mut adc1),
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dacs: (ref mut dac0, ref mut dac1),
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ref settings,
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ref mut telemetry,
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ref mut lockin,
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ref mut pll,
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ref mut timestamper,
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ref mut generator,
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ref mut signal_generator,
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} = c.resources;
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let (reference_phase, reference_frequency) = match settings.lockin_mode
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{
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LockinMode::External => {
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let timestamp = timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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let (pll_phase, pll_frequency) = pll.update(
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[1],
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);
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(pll_phase, (pll_frequency >> BATCH_SIZE_SIZE_LOG2) as i32)
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}
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LockinMode::Internal => {
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// Reference phase and frequency are known.
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(1i32 << 30, 1i32 << (32 - BATCH_SIZE_SIZE_LOG2))
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}
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};
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let sample_frequency =
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reference_frequency.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings.lockin_phase.wrapping_add(
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reference_phase.wrapping_mul(settings.lockin_harmonic),
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);
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(adc0, adc1, dac0, dac1).lock(|adc0, adc1, dac0, dac1| {
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let adc_samples = [adc0, adc1];
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let mut dac_samples = [dac0, dac1];
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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let output: Complex<i32> = adc_samples[0]
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.iter()
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// Zip in the LO phase.
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.zip(Accu::new(sample_phase, sample_frequency))
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// Convert to signed, MSB align the ADC sample, update the Lockin (demodulate, filter)
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.map(|(&sample, phase)| {
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let s = (sample as i16 as i32) << 16;
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lockin.update(s, phase, settings.lockin_tc)
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})
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// Decimate
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.last()
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.unwrap()
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* 2; // Full scale assuming the 2f component is gone.
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// Convert to DAC data.
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for (channel, samples) in dac_samples.iter_mut().enumerate() {
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for sample in samples.iter_mut() {
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let value = match settings.output_conf[channel] {
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Conf::Magnitude => output.abs_sqr() as i32 >> 16,
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Conf::Phase => output.arg() >> 16,
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Conf::LogPower => (output.log2() << 24) as i32 >> 16,
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Conf::ReferenceFrequency => {
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reference_frequency as i32 >> 16
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}
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Conf::InPhase => output.re >> 16,
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Conf::Quadrature => output.im >> 16,
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Conf::Modulation => {
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signal_generator.next().unwrap() as i32
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}
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};
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*sample = DacCode::from(value as i16).0;
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}
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}
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// Stream the data.
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const N: usize =
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(1 << BATCH_SIZE_SIZE_LOG2) * core::mem::size_of::<u16>();
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generator.add::<_, { N * 4 }>(|buf| {
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for (data, buf) in adc_samples
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.iter()
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.chain(dac_samples.iter())
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.zip(buf.chunks_exact_mut(N))
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{
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let data = unsafe {
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core::slice::from_raw_parts(
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data.as_ptr() as *const u8,
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N,
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)
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};
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buf.copy_from_slice(data)
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}
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});
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// Update telemetry measurements.
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telemetry.adcs =
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[AdcCode(adc_samples[0][0]), AdcCode(adc_samples[1][0])];
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telemetry.dacs =
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[DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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});
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}
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#[idle(resources=[network], spawn=[settings_update])]
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fn idle(mut c: idle::Context) -> ! {
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loop {
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match c.resources.network.lock(|net| net.update()) {
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NetworkState::SettingsChanged => {
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c.spawn.settings_update().unwrap()
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}
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NetworkState::Updated => {}
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NetworkState::NoChange => cortex_m::asm::wfi(),
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}
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}
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}
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#[task(priority = 1, resources=[network, settings, afes])]
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fn settings_update(mut c: settings_update::Context) {
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let settings = c.resources.network.miniconf.settings();
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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c.resources.settings.lock(|current| *current = *settings);
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let target = settings.stream_target.into();
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c.resources.network.direct_stream(target);
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}
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#[task(priority = 1, resources=[network, digital_inputs, settings, telemetry], schedule=[telemetry])]
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fn telemetry(mut c: telemetry::Context) {
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let mut telemetry: TelemetryBuffer =
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c.resources.telemetry.lock(|telemetry| *telemetry);
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telemetry.digital_inputs = [
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c.resources.digital_inputs.0.is_high().unwrap(),
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c.resources.digital_inputs.1.is_high().unwrap(),
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];
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let (gains, telemetry_period) = c
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.resources
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.settings
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.lock(|settings| (settings.afe, settings.telemetry_period));
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c.resources
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.network
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.telemetry
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.publish(&telemetry.finalize(gains[0], gains[1]));
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// Schedule the telemetry task in the future.
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c.schedule
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.telemetry(
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c.scheduled
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+ SystemTimer::ticks_from_secs(telemetry_period as u32),
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)
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.unwrap();
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}
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#[task(priority = 1, resources=[network], schedule=[ethernet_link])]
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fn ethernet_link(c: ethernet_link::Context) {
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c.resources.network.processor.handle_link();
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c.schedule
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.ethernet_link(c.scheduled + SystemTimer::ticks_from_secs(1))
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.unwrap();
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}
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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unsafe { hal::ethernet::interrupt_handler() }
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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