115 lines
4.2 KiB
Rust
115 lines
4.2 KiB
Rust
///! Stabilizer DAC output control
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///!
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///! Stabilizer output DACs do not currently rely on DMA requests for generating output.
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///! Instead, the DACs utilize an internal queue for storing output codes. A timer then periodically
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///! generates an interrupt which triggers an update of the DACs via a write over SPI.
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use super::hal;
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use heapless::consts;
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/// Controller structure for managing the DAC outputs.
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pub struct DacOutputs {
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dac0_spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
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dac1_spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
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timer: hal::timer::Timer<hal::stm32::TIM3>,
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// The queue is provided a default length of 32 updates, but this queue can be updated by the
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// end user to be larger if necessary.
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outputs: heapless::spsc::Queue<(u16, u16), consts::U32>,
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}
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impl DacOutputs {
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/// Construct a new set of DAC output controls
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///
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/// # Args
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/// * `dac0_spi` - The SPI interface to the DAC0 output.
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/// * `dac1_spi` - The SPI interface to the DAC1 output.
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/// * `timer` - The timer used to generate periodic events for updating the DACs.
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pub fn new(
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mut dac0_spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
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mut dac1_spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
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mut timer: hal::timer::Timer<hal::stm32::TIM3>,
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) -> Self {
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// Start the DAC SPI interfaces in infinite transaction mode. CS is configured in
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// auto-suspend mode.
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dac0_spi.inner().cr1.modify(|_, w| w.cstart().started());
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dac1_spi.inner().cr1.modify(|_, w| w.cstart().started());
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dac0_spi.listen(hal::spi::Event::Error);
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dac1_spi.listen(hal::spi::Event::Error);
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// Stop the timer and begin listening for timeouts. Timeouts will be used as a means to
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// generate new DAC outputs.
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timer.pause();
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timer.reset_counter();
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timer.clear_irq();
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timer.listen(hal::timer::Event::TimeOut);
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Self {
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dac0_spi,
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dac1_spi,
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outputs: heapless::spsc::Queue::new(),
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timer,
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}
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}
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/// Push a set of new DAC output codes to the internal queue.
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///
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/// # Note
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/// The earlier DAC output codes will be generated within 1 update cycle of the codes. This is a
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/// fixed latency currently.
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///
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/// This function will panic if too many codes are written.
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///
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/// # Args
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/// * `dac0_value` - The value to enqueue for a DAC0 update.
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/// * `dac1_value` - The value to enqueue for a DAC1 update.
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pub fn push(&mut self, dac0_value: u16, dac1_value: u16) {
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self.outputs.enqueue((dac0_value, dac1_value)).unwrap();
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self.timer.resume();
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}
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/// Update the DAC codes with the next set of values in the internal queue.
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///
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/// # Note
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/// This is intended to be called from the TIM3 update ISR.
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///
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/// If the last value in the queue is used, the timer is stopped.
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pub fn update(&mut self) {
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self.timer.clear_irq();
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match self.outputs.dequeue() {
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Some((dac0, dac1)) => self.write(dac0, dac1),
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None => {
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self.timer.pause();
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self.timer.reset_counter();
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self.timer.clear_irq();
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}
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};
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}
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/// Write immediate values to the DAC outputs.
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///
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/// # Note
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/// The DACs will be updated as soon as the SPI transfer completes, which will be nominally
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/// 320nS after this function call.
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///
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/// # Args
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/// * `dac0_value` - The output code to write to DAC0.
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/// * `dac1_value` - The output code to write to DAC1.
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pub fn write(&mut self, dac0_value: u16, dac1_value: u16) {
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// In order to optimize throughput and minimize latency, the DAC codes are written directly
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// into the SPI TX FIFO. No error checking is conducted. Errors are handled via interrupts
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// instead.
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unsafe {
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core::ptr::write_volatile(
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&self.dac0_spi.inner().txdr as *const _ as *mut u16,
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dac0_value,
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);
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core::ptr::write_volatile(
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&self.dac1_spi.inner().txdr as *const _ as *mut u16,
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dac1_value,
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);
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}
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}
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}
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