91f16c2961
Adding working example
2021-02-03 19:55:58 +01:00
738516eedb
Adding broken example
2021-02-03 15:13:37 +01:00
9e1a6ec4d5
Updating dependencies
2021-02-03 14:06:09 +01:00
913990d531
Merge remote-tracking branch 'origin/rj/bump-hal-smoltcp' into feature/mqtt-convert
2021-02-03 14:02:20 +01:00
672ddfa3c3
pounder: also adapt to new hal
2021-02-03 13:25:00 +01:00
c5fde8563c
deps: bump hal and smoltcp, adapt
2021-02-03 13:16:22 +01:00
e423eff0e2
lockin-external: add doc
2021-02-02 15:50:31 +01:00
bd71136cdf
hw/config: add TODO on synchronization
2021-02-02 15:46:50 +01:00
145b48074e
timers: remove spurious tim2 reset
2021-02-02 15:42:51 +01:00
ddbfa9d988
timestamping: docs and naming
2021-02-02 14:34:48 +01:00
e1c87c149f
timestamping_timer: also reset counter
2021-02-02 13:25:45 +01:00
854ed29b1a
timestamp: pass overflows to the top and ignore them there
2021-02-02 12:34:20 +01:00
4475a2d040
timestamping: full u32 range
...
The sampling timer and the timestamping timer have the same period.
The sampling interval and the batch size are powers of two.
If the timestamping timer wraps at a power of two larger than the
batch period, it will wrap in sync with the batch period.
Even if it didn't the RPLL would handle that. But it requires that the
timer wraps at the u32/i32 boundary (or be shifted left to wrap there).
2021-02-02 11:36:10 +01:00
2144af5bcd
configuration: update to HITL ips
2021-02-01 19:32:20 +01:00
24a4486847
lockin-internal: rotate samples
2021-02-01 19:31:57 +01:00
9ee60824d4
lockin-internal: align processing with lockin-external
2021-02-01 18:15:51 +01:00
f9b5d29450
lockin: de-nest processing flow
2021-02-01 18:14:09 +01:00
b6e22b576b
iir: add const fn new()
2021-02-01 17:18:10 +01:00
656e3253ab
lockin-internal: document, streamline sequence
2021-02-01 17:09:06 +01:00
65a3f839a0
lockin: remove feed()
2021-02-01 13:42:38 +01:00
2c60103696
dsp: accu: add, iir: rename IIRState to Vec5
2021-02-01 12:23:47 +01:00
46a7d67027
lockin-internal: rename, adapt
2021-01-31 19:26:11 +01:00
6e1444f070
Merge pull request #247 from quartiq/dsp-iir-benches
...
Dsp iir benches
2021-01-31 19:24:56 +01:00
8dc811da11
Merge pull request #240 from vertigo-designs/feature/lockin-app-refactor
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Adding internal lock-in integration demo
2021-01-31 19:14:08 +01:00
47089c267c
dsp: align iir and iir_int, add iir micro benches
2021-01-31 19:12:24 +01:00
80055076b8
lockin: scale output
2021-01-31 17:41:20 +01:00
82c8fa1a07
rpll: extend tests
2021-01-31 17:10:03 +01:00
ab20d67a07
rpll: remove redundant time tracking
2021-01-31 13:42:15 +01:00
096f786795
Expanding miniconf to lockin
2021-01-30 18:57:06 +01:00
411a847a88
Updating smoltcp-nal
2021-01-30 18:48:27 +01:00
0d1b237202
complex: richer API
2021-01-30 18:05:54 +01:00
9a1bb5da91
Fixing build
2021-01-30 15:07:26 +01:00
b73286c188
Removing MQTT interface
2021-01-30 15:00:58 +01:00
e954ba3c52
Merge branch 'master' into feature/mqtt-convert
2021-01-30 14:48:54 +01:00
8b46c3c768
Updating internal lockin demo
2021-01-29 18:55:54 +01:00
b152343aaf
Style
2021-01-29 11:05:46 +01:00
ab7d725235
Updating lockin demo after testing
2021-01-29 11:01:21 +01:00
1ebbe0f6d7
Cleaning up demo
2021-01-29 10:11:56 +01:00
cf8b06be81
Merge branch 'master' into feature/lockin-app-refactor
2021-01-29 10:06:45 +01:00
Ryan Summers
c628b8d57a
Update src/bin/lockin-internal-demo.rs
...
Co-authored-by: Robert Jördens <rj@quartiq.de>
2021-01-29 09:55:23 +01:00
c34e330663
lockin: fmt
2021-01-28 23:00:55 +01:00
36288225b3
rpll: extend to above-nyquist frequencies
2021-01-28 22:21:42 +01:00
702ccc231d
Using custom branch of miniconf
2021-01-27 18:15:35 +01:00
1749d48ca3
Revert "rpll: auto-align counter"
...
This reverts commit dbacc5293e12f712fef7bd85848e1b0bd8fde823.
2021-01-27 09:01:07 +01:00
45e7d6de3c
rpll: auto-align counter
2021-01-27 09:01:07 +01:00
a772ccc38a
Adding WIP updates for StringSet
2021-01-26 19:14:23 +01:00
7b9fc3b2b3
iir_int: move lowpass coefficient calculation to iirstate
2021-01-26 18:51:20 +01:00
ea7b08fc64
rpll: refine
2021-01-26 14:40:44 +01:00
f0e7c153ba
Adding WIP refactor for MQTT + settings
2021-01-26 14:28:06 +01:00
Ryan Summers
c030b97714
Apply suggestions from code review
...
Co-authored-by: Robert Jördens <rj@quartiq.de>
2021-01-26 12:49:45 +01:00
