From fc93de432db700cd9ef024761b429535810523b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Wed, 11 Sep 2019 15:35:06 +0200 Subject: [PATCH] enable cycle counter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit c.f. japaric/cortex-m-rtfm#184 Signed-off-by: Robert Jördens --- src/main.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main.rs b/src/main.rs index ac9a075..515933c 100644 --- a/src/main.rs +++ b/src/main.rs @@ -555,7 +555,7 @@ const APP: () = { cp.SCB.enable_icache(); // TODO: ETH DMA coherence issues // cp.SCB.enable_dcache(&mut cp.CPUID); - // cp.DWT.enable_cycle_counter(); + cp.DWT.enable_cycle_counter(); // japaric/cortex-m-rtfm#184 rcc.ahb4enr.modify(|_, w| w.gpioaen().set_bit()