From f8fa297b20f0bb4f1948972ce13e926f1ddae650 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Tue, 1 Jun 2021 14:49:51 +0200
Subject: [PATCH] lockin: dma fence

---
 src/bin/lockin.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/bin/lockin.rs b/src/bin/lockin.rs
index 54ce37b..dd20278 100644
--- a/src/bin/lockin.rs
+++ b/src/bin/lockin.rs
@@ -2,6 +2,8 @@
 #![no_std]
 #![no_main]
 
+use core::sync::atomic::{fence, Ordering};
+
 use embedded_hal::digital::v2::InputPin;
 
 use serde::Deserialize;
@@ -214,6 +216,9 @@ const APP: () = {
             let adc_samples = [adc0, adc1];
             let mut dac_samples = [dac0, dac1];
 
+            // Preserve instruction and data ordering w.r.t. DMA flag access.
+            fence(Ordering::SeqCst);
+
             let output: Complex<i32> = adc_samples[0]
                 .iter()
                 // Zip in the LO phase.
@@ -252,6 +257,9 @@ const APP: () = {
 
             telemetry.dacs =
                 [DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
+
+            // Preserve instruction and data ordering w.r.t. DMA flag access.
+            fence(Ordering::SeqCst);
         });
     }