From f825f527850712aa65185303bbb8e548feffe6d5 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 6 Jan 2021 06:08:07 -0800 Subject: [PATCH] Apply suggestions from code review MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Robert Jördens --- src/adc.rs | 4 ++-- src/dac.rs | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index a652d3d..09f1b05 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -49,7 +49,7 @@ ///! ///! The ADCs collect a group of N samples, which is referred to as a batch. The size of the batch ///! is configured by the user at compile-time to allow for a custom-tailored implementation. Larger -///! batch sizes generally provide for more processing time per sample, but come at the expense of +///! batch sizes generally provide for lower overhead and more processing time per sample, but come at the expense of ///! increased input -> output latency. ///! ///! @@ -69,7 +69,7 @@ ///! In this implementation, single buffer mode DMA transfers are used because the SPI RX FIFO can ///! be used as a means to both detect and buffer ADC samples during the buffer swap-over. Because ///! of this, double-buffered mode does not offer any advantages over single-buffered mode (unless -///! double-buffered mode offers less overhead when accessing data). +///! double-buffered mode offers less overhead due to the DMA disable/enable procedure). use super::{ hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE, diff --git a/src/dac.rs b/src/dac.rs index 53076b0..22f33fa 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -14,14 +14,14 @@ ///! the DAC without requiring the CPU. ///! ///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC -///! output batch is always exactly 1 batch after the ADC batch that generated it. +///! output batch is always exactly 2 batches after the ADC batch that generated it. ///! ///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any ///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA -///! transfer completion is handled). In this mode, there should always be a valid buffer in the +///! transfer completion is handled). In this mode, by the time DMA swaps buffers, there is always a valid buffer in the ///! "next-transfer" double-buffer location for the DMA transfer. Once a transfer completes, -///! software then has exactly one batch duration to properly configure the next buffer before it -///! begins transfer. +///! software then has exactly one batch duration to fill the next buffer before its +///! transfer begins. ///! ///! ## Multiple Samples to Single DAC Codes ///!