From f47ee38d314f906710da7fd0f0d8473eee3cf2d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 4 Feb 2021 12:48:25 +0100 Subject: [PATCH] move sample ticks and buffer size to design parameters --- src/bin/lockin-external.rs | 14 ++++++++------ src/bin/lockin-internal.rs | 7 ++++--- src/hardware/adc.rs | 4 ++-- src/hardware/configuration.rs | 19 +++++++++---------- src/hardware/dac.rs | 4 ++-- src/hardware/design_parameters.rs | 10 ++++++++++ src/hardware/mod.rs | 2 +- src/lib.rs | 10 ---------- 8 files changed, 36 insertions(+), 34 deletions(-) diff --git a/src/bin/lockin-external.rs b/src/bin/lockin-external.rs index d3b3410..ae25d15 100644 --- a/src/bin/lockin-external.rs +++ b/src/bin/lockin-external.rs @@ -11,9 +11,7 @@ use rtic::cyccnt::{Instant, U32Ext}; use heapless::{consts::*, String}; -use stabilizer::{ - hardware, server, ADC_SAMPLE_TICKS_LOG2, SAMPLE_BUFFER_SIZE_LOG2, -}; +use stabilizer::{hardware, hardware::design_parameters, server}; use dsp::{iir, iir_int, lockin::Lockin, rpll::RPLL, Accu}; use hardware::{ @@ -52,7 +50,10 @@ const APP: () = { // Configure the microcontroller let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device); - let pll = RPLL::new(ADC_SAMPLE_TICKS_LOG2 + SAMPLE_BUFFER_SIZE_LOG2); + let pll = RPLL::new( + design_parameters::ADC_SAMPLE_TICKS_LOG2 + + design_parameters::SAMPLE_BUFFER_SIZE_LOG2, + ); let lockin = Lockin::new( iir_int::Vec5::lowpass(1e-3, 0.707, 2.), // TODO: expose @@ -126,8 +127,9 @@ const APP: () = { let phase_offset: i32 = 0; // TODO: expose let sample_frequency = ((pll_frequency - // .wrapping_add(1 << SAMPLE_BUFFER_SIZE_LOG2 - 1) // half-up rounding bias - >> SAMPLE_BUFFER_SIZE_LOG2) as i32) + // .wrapping_add(1 << design_parameters::SAMPLE_BUFFER_SIZE_LOG2 - 1) // half-up rounding bias + >> design_parameters::SAMPLE_BUFFER_SIZE_LOG2) + as i32) .wrapping_mul(harmonic); let sample_phase = phase_offset.wrapping_add(pll_phase.wrapping_mul(harmonic)); diff --git a/src/bin/lockin-internal.rs b/src/bin/lockin-internal.rs index 4974be2..cadf189 100644 --- a/src/bin/lockin-internal.rs +++ b/src/bin/lockin-internal.rs @@ -4,13 +4,13 @@ use dsp::{iir_int, lockin::Lockin, Accu}; use hardware::{Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1}; -use stabilizer::{hardware, SAMPLE_BUFFER_SIZE, SAMPLE_BUFFER_SIZE_LOG2}; +use stabilizer::{hardware, hardware::design_parameters}; // A constant sinusoid to send on the DAC output. // Full-scale gives a +/- 10V amplitude waveform. Scale it down to give +/- 1V. const ONE: i16 = (0.1 * u16::MAX as f32) as _; const SQRT2: i16 = (ONE as f32 * 0.707) as _; -const DAC_SEQUENCE: [i16; SAMPLE_BUFFER_SIZE] = +const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] = [ONE, SQRT2, 0, -SQRT2, -ONE, -SQRT2, 0, SQRT2]; #[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] @@ -83,7 +83,8 @@ const APP: () = { // Reference phase and frequency are known. let pll_phase = 0; - let pll_frequency = 1i32 << (32 - SAMPLE_BUFFER_SIZE_LOG2); + let pll_frequency = + 1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2); // Harmonic index of the LO: -1 to _de_modulate the fundamental let harmonic: i32 = -1; diff --git a/src/hardware/adc.rs b/src/hardware/adc.rs index 1cb6c17..3f2fa5d 100644 --- a/src/hardware/adc.rs +++ b/src/hardware/adc.rs @@ -74,9 +74,9 @@ ///! double-buffered mode offers less overhead due to the DMA disable/enable procedure). use stm32h7xx_hal as hal; -use crate::SAMPLE_BUFFER_SIZE; - +use super::design_parameters::SAMPLE_BUFFER_SIZE; use super::timers; + use hal::dma::{ config::Priority, dma::{DMAReq, DmaConfig}, diff --git a/src/hardware/configuration.rs b/src/hardware/configuration.rs index e173dc7..0b4b156 100644 --- a/src/hardware/configuration.rs +++ b/src/hardware/configuration.rs @@ -1,11 +1,6 @@ ///! Stabilizer hardware configuration ///! ///! This file contains all of the hardware-specific configuration of Stabilizer. -use crate::ADC_SAMPLE_TICKS; - -#[cfg(feature = "pounder_v1_1")] -use crate::SAMPLE_BUFFER_SIZE; - #[cfg(feature = "pounder_v1_1")] use core::convert::TryInto; @@ -157,7 +152,8 @@ pub fn setup( timer2.set_tick_freq(design_parameters::TIMER_FREQUENCY); let mut sampling_timer = timers::SamplingTimer::new(timer2); - sampling_timer.set_period_ticks((ADC_SAMPLE_TICKS - 1) as u32); + sampling_timer + .set_period_ticks((design_parameters::ADC_SAMPLE_TICKS - 1) as u32); // The sampling timer is used as the master timer for the shadow-sampling timer. Thus, // it generates a trigger whenever it is enabled. @@ -181,7 +177,8 @@ pub fn setup( let mut shadow_sampling_timer = timers::ShadowSamplingTimer::new(timer3); - shadow_sampling_timer.set_period_ticks(ADC_SAMPLE_TICKS - 1); + shadow_sampling_timer + .set_period_ticks(design_parameters::ADC_SAMPLE_TICKS - 1); // The shadow sampling timer is a slave-mode timer to the sampling timer. It should // always be in-sync - thus, we configure it to operate in slave mode using "Trigger @@ -726,7 +723,8 @@ pub fn setup( let sample_frequency = { let timer_frequency: hal::time::Hertz = design_parameters::TIMER_FREQUENCY.into(); - timer_frequency.0 as f32 / ADC_SAMPLE_TICKS as f32 + timer_frequency.0 as f32 + / design_parameters::ADC_SAMPLE_TICKS as f32 }; let sample_period = 1.0 / sample_frequency; @@ -773,8 +771,9 @@ pub fn setup( }; let period = (tick_ratio - * ADC_SAMPLE_TICKS as f32 - * SAMPLE_BUFFER_SIZE as f32) as u32 + * design_parameters::ADC_SAMPLE_TICKS as f32 + * design_parameters::SAMPLE_BUFFER_SIZE as f32) + as u32 / 4; timestamp_timer.set_period_ticks((period - 1).try_into().unwrap()); let tim8_channels = timestamp_timer.channels(); diff --git a/src/hardware/dac.rs b/src/hardware/dac.rs index 5ca65fb..d41ae8c 100644 --- a/src/hardware/dac.rs +++ b/src/hardware/dac.rs @@ -52,9 +52,9 @@ ///! served promptly after the transfer completes. use stm32h7xx_hal as hal; -use crate::SAMPLE_BUFFER_SIZE; - +use super::design_parameters::SAMPLE_BUFFER_SIZE; use super::timers; + use hal::dma::{ dma::{DMAReq, DmaConfig}, traits::TargetAddress, diff --git a/src/hardware/design_parameters.rs b/src/hardware/design_parameters.rs index 3de7c15..9951ee5 100644 --- a/src/hardware/design_parameters.rs +++ b/src/hardware/design_parameters.rs @@ -39,3 +39,13 @@ pub const DDS_SYSTEM_CLK: MegaHertz = /// The divider from the DDS system clock to the SYNC_CLK output (sync-clk is always 1/4 of sysclk). #[allow(dead_code)] pub const DDS_SYNC_CLK_DIV: u8 = 4; + +// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is +// equal to 10ns per tick. +// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz +pub const ADC_SAMPLE_TICKS_LOG2: u8 = 8; +pub const ADC_SAMPLE_TICKS: u16 = 1 << ADC_SAMPLE_TICKS_LOG2; + +// The desired ADC sample processing buffer size. +pub const SAMPLE_BUFFER_SIZE_LOG2: u8 = 3; +pub const SAMPLE_BUFFER_SIZE: usize = 1 << SAMPLE_BUFFER_SIZE_LOG2; diff --git a/src/hardware/mod.rs b/src/hardware/mod.rs index f912057..b54b6f7 100644 --- a/src/hardware/mod.rs +++ b/src/hardware/mod.rs @@ -11,7 +11,7 @@ mod adc; mod afe; mod configuration; mod dac; -mod design_parameters; +pub mod design_parameters; mod digital_input_stamper; mod eeprom; mod pounder; diff --git a/src/lib.rs b/src/lib.rs index ab2623d..c252f37 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -6,13 +6,3 @@ extern crate log; pub mod hardware; pub mod server; - -// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is -// equal to 10ns per tick. -// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz -pub const ADC_SAMPLE_TICKS_LOG2: u8 = 8; -pub const ADC_SAMPLE_TICKS: u16 = 1 << ADC_SAMPLE_TICKS_LOG2; - -// The desired ADC sample processing buffer size. -pub const SAMPLE_BUFFER_SIZE_LOG2: u8 = 3; -pub const SAMPLE_BUFFER_SIZE: usize = 1 << SAMPLE_BUFFER_SIZE_LOG2;