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pounder_test
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pac updates (~0.8)

This commit is contained in:
Robert Jördens 2019-05-06 17:09:49 +00:00
parent 86dbdf98e2
commit f1c43c6492
2 changed files with 92 additions and 96 deletions
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7
Cargo.toml
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@ -30,14 +30,17 @@ default-target = "thumbv7em-none-eabihf"
cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] } cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] }
cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-rt = { version = "0.6", features = ["device"] }
cortex-m-log = { version = "0.5", features = ["log-integration"] } cortex-m-log = { version = "0.5", features = ["log-integration"] }
stm32h7 = { path = "../stm32-rs/stm32h7", features = ["stm32h7x3", "rt"] }
log = "0.4" log = "0.4"
panic-abort = "0.3" panic-abort = "0.3"
panic-semihosting = { version = "0.5.2", optional = true } panic-semihosting = { version = "0.5.2", optional = true }
[dependencies.stm32h7]
path = "../stm32-rs/stm32h7"
# version = "0.7"
features = ["stm32h7x3", "rt"]
[dependencies.smoltcp] [dependencies.smoltcp]
#git = "https://github.com/m-labs/smoltcp" #git = "https://github.com/m-labs/smoltcp"
#rev = "cd893e6"
version = "0.5" version = "0.5"
features = ["proto-ipv4", "socket-tcp"] features = ["proto-ipv4", "socket-tcp"]
default-features = false default-features = false

181
src/main.rs
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@ -333,85 +333,81 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
// ADC0 // ADC0
fn spi1_setup(spi1: &stm32::SPI1) { fn spi1_setup(spi1: &stm32::SPI1) {
spi1.cfg1.modify(|_, w| { spi1.cfg1.modify(|_, w|
w.mbr().bits(1) // clk/4 w.mbr().div4()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthlv().one_frame() .fthlv().one_frame()
}); );
spi1.cfg2.modify(|_, w| unsafe { spi1.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().set_bit() .cpol().idle_high()
.cpha().set_bit() .cpha().second_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b10) // simplex receiver .comm().receiver()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(6) // master SS idle .mssi().bits(6)
}); );
spi1.cr2.modify(|_, w| { spi1.cr2.modify(|_, w| w.tsize().bits(1));
w.tsize().bits(1)
});
spi1.cr1.write(|w| w.spe().set_bit()); spi1.cr1.write(|w| w.spe().set_bit());
} }
// ADC1 // ADC1
fn spi5_setup(spi5: &stm32::SPI5) { fn spi5_setup(spi5: &stm32::SPI5) {
spi5.cfg1.modify(|_, w| { spi5.cfg1.modify(|_, w|
w.mbr().bits(1) // clk/4 w.mbr().div4()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthlv().one_frame() .fthlv().one_frame()
}); );
spi5.cfg2.modify(|_, w| unsafe { spi5.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().set_bit() .cpol().idle_high()
.cpha().set_bit() .cpha().second_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b10) // simplex receiver .comm().receiver()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(6) // master SS idle .mssi().bits(6)
}); );
spi5.cr2.modify(|_, w| { spi5.cr2.modify(|_, w| w.tsize().bits(1));
w.tsize().bits(1)
});
spi5.cr1.write(|w| w.spe().set_bit()); spi5.cr1.write(|w| w.spe().set_bit());
} }
// DAC0 // DAC0
fn spi2_setup(spi2: &stm32::SPI2) { fn spi2_setup(spi2: &stm32::SPI2) {
spi2.cfg1.modify(|_, w| { spi2.cfg1.modify(|_, w|
w.mbr().bits(0) // clk/2 w.mbr().div2()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthlv().one_frame() .fthlv().one_frame()
}); );
spi2.cfg2.modify(|_, w| unsafe { spi2.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().clear_bit() .cpol().idle_low()
.cpha().clear_bit() .cpha().first_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b01) // simplex transmitter .comm().transmitter()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(0) // master SS idle .mssi().bits(0)
}); );
spi2.cr2.modify(|_, w| w.tsize().bits(0)); spi2.cr2.modify(|_, w| w.tsize().bits(0));
spi2.cr1.write(|w| w.spe().enabled()); spi2.cr1.write(|w| w.spe().enabled());
spi2.cr1.modify(|_, w| w.cstart().started()); spi2.cr1.modify(|_, w| w.cstart().started());
@ -419,30 +415,28 @@ fn spi2_setup(spi2: &stm32::SPI2) {
// DAC1 // DAC1
fn spi4_setup(spi4: &stm32::SPI4) { fn spi4_setup(spi4: &stm32::SPI4) {
spi4.cfg1.modify(|_, w| { spi4.cfg1.modify(|_, w|
w.mbr().bits(0) // clk/2 w.mbr().div2()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthlv().one_frame() .fthlv().one_frame()
}); );
spi4.cfg2.modify(|_, w| unsafe { spi4.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().clear_bit() .cpol().idle_low()
.cpha().clear_bit() .cpha().first_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b01) // simplex transmitter .comm().transmitter()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(0) // master SS idle .mssi().bits(0)
}); );
spi4.cr2.modify(|_, w| { spi4.cr2.modify(|_, w| w.tsize().bits(0));
w.tsize().bits(0)
});
spi4.cr1.write(|w| w.spe().enabled()); spi4.cr1.write(|w| w.spe().enabled());
spi4.cr1.modify(|_, w| w.cstart().started()); spi4.cr1.modify(|_, w| w.cstart().started());
} }
@ -461,10 +455,10 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); dma1.st[0].cr.modify(|_, w| w.en().clear_bit());
while dma1.st[0].cr.read().en().bit_is_set() {} while dma1.st[0].cr.read().en().bit_is_set() {}
dma1.st[0].par.write(|w| unsafe { w.pa().bits(pa0 as u32) }); dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) });
dma1.st[0].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) });
dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) }); dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) });
dmamux1.ccr[0].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up());
dma1.st[0].cr.modify(|_, w| unsafe { dma1.st[0].cr.modify(|_, w| unsafe {
w.pl().bits(0b01) // medium w.pl().bits(0b01) // medium
.circ().set_bit() // reload ndtr .circ().set_bit() // reload ndtr
@ -484,10 +478,10 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
dma1.st[1].cr.modify(|_, w| w.en().clear_bit()); dma1.st[1].cr.modify(|_, w| w.en().clear_bit());
while dma1.st[1].cr.read().en().bit_is_set() {} while dma1.st[1].cr.read().en().bit_is_set() {}
dma1.st[1].par.write(|w| unsafe { w.pa().bits(pa1 as u32) }); dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) });
dma1.st[1].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) });
dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) }); dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) });
dmamux1.ccr[1].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up());
dma1.st[1].cr.modify(|_, w| unsafe { dma1.st[1].cr.modify(|_, w| unsafe {
w.pl().bits(0b01) // medium w.pl().bits(0b01) // medium
.circ().set_bit() // reload ndtr .circ().set_bit() // reload ndtr
@ -611,9 +605,8 @@ fn main() -> ! {
rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
// work around the SPI stall erratum // work around the SPI stall erratum
//let dbgmcu = dp.DBGMCU; let dbgmcu = dp.DBGMCU;
//dbgmcu.apb1lfz1.modify(|_, w| w.stop_tim2().set_bit()); // stop tim2 in debug dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit());
unsafe { ptr::write_volatile(0x5c00_103c as *mut usize, 0x0000_0001) };
unsafe { unsafe {
let t = 2e-6*2.; let t = 2e-6*2.;