From f19988a1bdb7102a0f6669519f1047ea1fe55576 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Thu, 4 Feb 2021 15:42:45 +0100
Subject: [PATCH] up the sample rate

---
 src/hardware/design_parameters.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/hardware/design_parameters.rs b/src/hardware/design_parameters.rs
index 9951ee5..ddc0614 100644
--- a/src/hardware/design_parameters.rs
+++ b/src/hardware/design_parameters.rs
@@ -42,8 +42,8 @@ pub const DDS_SYNC_CLK_DIV: u8 = 4;
 
 // The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
 // equal to 10ns per tick.
-// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
-pub const ADC_SAMPLE_TICKS_LOG2: u8 = 8;
+// Currently, the sample rate is equal to: Fsample = 100/128 MHz ~ 800 KHz
+pub const ADC_SAMPLE_TICKS_LOG2: u8 = 7;
 pub const ADC_SAMPLE_TICKS: u16 = 1 << ADC_SAMPLE_TICKS_LOG2;
 
 // The desired ADC sample processing buffer size.