From ee8f4d849f51274de5f45a7c2b7f10e540032186 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 17 Dec 2020 14:32:53 +0100 Subject: [PATCH] Adding documentation about double-buffered mode to DACs --- src/dac.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/dac.rs b/src/dac.rs index 3e44379..53076b0 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -13,6 +13,16 @@ ///! configuring a DMA stream for a number of successive DAC codes, hardware can regularly update ///! the DAC without requiring the CPU. ///! +///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC +///! output batch is always exactly 1 batch after the ADC batch that generated it. +///! +///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any +///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA +///! transfer completion is handled). In this mode, there should always be a valid buffer in the +///! "next-transfer" double-buffer location for the DMA transfer. Once a transfer completes, +///! software then has exactly one batch duration to properly configure the next buffer before it +///! begins transfer. +///! ///! ## Multiple Samples to Single DAC Codes ///! ///! For some applications, it may be desirable to generate a single DAC code from multiple ADC