Adding documentation about double-buffered mode to DACs
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src/dac.rs
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src/dac.rs
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///! configuring a DMA stream for a number of successive DAC codes, hardware can regularly update
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///! the DAC without requiring the CPU.
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///!
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///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC
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///! output batch is always exactly 1 batch after the ADC batch that generated it.
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///!
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///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any
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///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA
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///! transfer completion is handled). In this mode, there should always be a valid buffer in the
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///! "next-transfer" double-buffer location for the DMA transfer. Once a transfer completes,
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///! software then has exactly one batch duration to properly configure the next buffer before it
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///! begins transfer.
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///!
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///! ## Multiple Samples to Single DAC Codes
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///!
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///! For some applications, it may be desirable to generate a single DAC code from multiple ADC
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