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Adding documentation about double-buffered mode to DACs

master
Ryan Summers 2020-12-17 14:32:53 +01:00
parent fb1ea765ce
commit ee8f4d849f
1 changed files with 10 additions and 0 deletions
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src/dac.rs
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@ -13,6 +13,16 @@
///! configuring a DMA stream for a number of successive DAC codes, hardware can regularly update
///! the DAC without requiring the CPU.
///!
///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC
///! output batch is always exactly 1 batch after the ADC batch that generated it.
///!
///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any
///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA
///! transfer completion is handled). In this mode, there should always be a valid buffer in the
///! "next-transfer" double-buffer location for the DMA transfer. Once a transfer completes,
///! software then has exactly one batch duration to properly configure the next buffer before it
///! begins transfer.
///!
///! ## Multiple Samples to Single DAC Codes
///!
///! For some applications, it may be desirable to generate a single DAC code from multiple ADC