diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index e8e0e4e..9d0c2fe 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -85,6 +85,12 @@ jobs: target/*/release/stabilizer stabilizer-release.bin + - name: Build (Pounder v1.1) + uses: actions-rs/cargo@v1 + with: + command: build + args: --features ${{ matrix.features }} + test: runs-on: ubuntu-latest strategy: diff --git a/src/design_parameters.rs b/src/design_parameters.rs index f6222d2..3788764 100644 --- a/src/design_parameters.rs +++ b/src/design_parameters.rs @@ -21,19 +21,19 @@ pub const POUNDER_IO_UPDATE_DELAY: f32 = 900_e-9; /// The duration to assert IO_Update for the pounder DDS. // IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile write. With pounder -// SYNC_CLK running at 100MHz (1/4 of the pounder reference clock of 400MHz), this corresponds to -// 40ns. To accomodate rounding errors, we use 50ns instead. +// SYNC_CLK running at 100MHz (1/4 of the pounder reference clock of 500MHz), this corresponds to +// 32ns. To accomodate rounding errors, we use 50ns instead. pub const POUNDER_IO_UPDATE_DURATION: f32 = 50_e-9; /// The DDS reference clock frequency in MHz. -pub const DDS_REF_CLK_MHZ: u32 = 100; +pub const DDS_REF_CLK: MegaHertz = MegaHertz(100); /// The multiplier used for the DDS reference clock PLL. pub const DDS_MULTIPLIER: u8 = 5; /// The DDS system clock frequency after the internal PLL multiplication. -pub const DDS_SYSTEM_CLK_MHZ: u32 = DDS_REF_CLK_MHZ * DDS_MULTIPLIER as u32; +pub const DDS_SYSTEM_CLK: MegaHertz = + MegaHertz(DDS_REF_CLK.0 * DDS_MULTIPLIER as u32); -/// The rate of the DDS SYNC_CLK in MHz is always 1/4 that of the internal PLL clock. -#[allow(dead_code)] -pub const DDS_SYNC_CLK_MHZ: u32 = DDS_SYSTEM_CLK_MHZ / 4; +/// The divider from the DDS system clock to the SYNC_CLK output (sync-clk is always 1/4 of sysclk). +pub const DDS_SYNC_CLK_DIV: u8 = 4; diff --git a/src/main.rs b/src/main.rs index c01c27d..2684eed 100644 --- a/src/main.rs +++ b/src/main.rs @@ -30,6 +30,8 @@ extern crate panic_halt; #[macro_use] extern crate log; +use core::convert::TryInto; + // use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; use cortex_m_rt::exception; use rtic::cyccnt::{Instant, U32Ext}; @@ -562,13 +564,16 @@ const APP: () = { let mut io_update = gpiog.pg7.into_push_pull_output(); + let ref_clk: hal::time::Hertz = + design_parameters::DDS_REF_CLK.into(); + let ad9959 = ad9959::Ad9959::new( qspi_interface, reset_pin, &mut io_update, &mut delay, ad9959::Mode::FourBitSerial, - design_parameters::DDS_REF_CLK_MHZ as f32 * 1_000_000_f32, + ref_clk.0 as f32, design_parameters::DDS_MULTIPLIER, ) .unwrap(); @@ -850,13 +855,18 @@ const APP: () = { timestamp_timer.start(); // We want the pounder timestamp timer to overflow once per batch. - let tick_ratio = design_parameters::DDS_SYNC_CLK_MHZ as f32 - / design_parameters::TIMER_FREQUENCY_MHZ as f32; + let tick_ratio = { + let sync_clk_mhz: f32 = design_parameters::DDS_SYSTEM_CLK.0 + as f32 + / design_parameters::DDS_SYNC_CLK_DIV as f32; + sync_clk_mhz / design_parameters::TIMER_FREQUENCY.0 as f32 + }; + let period = (tick_ratio * ADC_SAMPLE_TICKS as f32 * SAMPLE_BUFFER_SIZE as f32) as u32 / 4; - timestamp_timer.set_period((period - 1).try_into().unwrap()); + timestamp_timer.set_period_ticks((period - 1).try_into().unwrap()); let tim8_channels = timestamp_timer.channels(); let stamper = pounder::timestamp::Timestamper::new(