From dd3f293cca606ff2d21555fc513cf89794238043 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 8 Apr 2021 14:17:38 +0200 Subject: [PATCH 1/5] Fixing ACR write padding --- ad9959/src/lib.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index 206d90a..f5d80a9 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -582,7 +582,9 @@ impl ProfileSerializer { } if let Some(acr) = acr { - self.add_write(Register::ACR, &acr.to_be_bytes()); + let mut data = [0; 3]; + data[1..=2].copy_from_slice(&acr.to_be_bytes()); + self.add_write(Register::ACR, &data); } } From bf3dae814da274052c05f4dde3d3a835fe907af5 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 8 Apr 2021 14:58:28 +0200 Subject: [PATCH 2/5] Updating ACR to 32-bit --- ad9959/src/lib.rs | 11 +++++------ src/hardware/pounder/dds_output.rs | 5 +++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index f5d80a9..a8fc48e 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -558,13 +558,14 @@ impl ProfileSerializer { /// * `channels` - A list of channels to apply the configuration to. /// * `ftw` - If provided, indicates a frequency tuning word for the channels. /// * `pow` - If provided, indicates a phase offset word for the channels. - /// * `acr` - If provided, indicates the amplitude control register for the channels. + /// * `acr` - If provided, indicates the amplitude control register for the channels. The ACR + /// should be stored in the 3 LSB of the word. pub fn update_channels( &mut self, channels: &[Channel], ftw: Option, pow: Option, - acr: Option, + acr: Option, ) { let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8); for channel in channels.iter() { @@ -582,9 +583,7 @@ impl ProfileSerializer { } if let Some(acr) = acr { - let mut data = [0; 3]; - data[1..=2].copy_from_slice(&acr.to_be_bytes()); - self.add_write(Register::ACR, &data); + self.add_write(Register::ACR, &acr.to_be_bytes()[1..=4]); } } @@ -608,7 +607,6 @@ impl ProfileSerializer { // Pad the buffer to 32-bit alignment by adding dummy writes to CSR and LSRR. let padding = 4 - (self.index % 4); match padding { - 0 => {} 1 => { // For a pad size of 1, we have to pad with 5 bytes to align things. self.add_write(Register::CSR, &[(self.mode as u8) << 1]); @@ -616,6 +614,7 @@ impl ProfileSerializer { } 2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]), 3 => self.add_write(Register::LSRR, &[0, 0, 0]), + 4 => {} _ => unreachable!(), } diff --git a/src/hardware/pounder/dds_output.rs b/src/hardware/pounder/dds_output.rs index c7c5e6d..e755482 100644 --- a/src/hardware/pounder/dds_output.rs +++ b/src/hardware/pounder/dds_output.rs @@ -144,14 +144,15 @@ impl<'a> ProfileBuilder<'a> { /// * `channels` - A list of channels to apply the configuration to. /// * `ftw` - If provided, indicates a frequency tuning word for the channels. /// * `pow` - If provided, indicates a phase offset word for the channels. - /// * `acr` - If provided, indicates the amplitude control register for the channels. + /// * `acr` - If provided, indicates the amplitude control register for the channels. The + /// 24-bits of the ACR should be stored in the last 3 LSB. #[allow(dead_code)] pub fn update_channels( mut self, channels: &[Channel], ftw: Option, pow: Option, - acr: Option, + acr: Option, ) -> Self { self.serializer.update_channels(channels, ftw, pow, acr); self From 4a2d4af5088ec91f78097bed80f3b7efc303c1ec Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 8 Apr 2021 15:00:30 +0200 Subject: [PATCH 3/5] Fixing end index --- ad9959/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index a8fc48e..9b7d77b 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -583,7 +583,7 @@ impl ProfileSerializer { } if let Some(acr) = acr { - self.add_write(Register::ACR, &acr.to_be_bytes()[1..=4]); + self.add_write(Register::ACR, &acr.to_be_bytes()[1..=3]); } } From 35aa3eb606fde3c090418512c67b1d724c064269 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 8 Apr 2021 15:04:34 +0200 Subject: [PATCH 4/5] Fixing other AD9959 profile issues --- ad9959/src/lib.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index 9b7d77b..89192b6 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -610,10 +610,10 @@ impl ProfileSerializer { 1 => { // For a pad size of 1, we have to pad with 5 bytes to align things. self.add_write(Register::CSR, &[(self.mode as u8) << 1]); - self.add_write(Register::LSRR, &[0, 0, 0]); + self.add_write(Register::LSRR, &[0, 0]); } 2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]), - 3 => self.add_write(Register::LSRR, &[0, 0, 0]), + 3 => self.add_write(Register::LSRR, &[0, 0]), 4 => {} _ => unreachable!(), From 090ec4650d5817f9770cfebbff1e2528dd090815 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 8 Apr 2021 16:05:51 +0200 Subject: [PATCH 5/5] Update ad9959/src/lib.rs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Robert Jördens --- ad9959/src/lib.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index 89192b6..21dfa21 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -559,7 +559,8 @@ impl ProfileSerializer { /// * `ftw` - If provided, indicates a frequency tuning word for the channels. /// * `pow` - If provided, indicates a phase offset word for the channels. /// * `acr` - If provided, indicates the amplitude control register for the channels. The ACR - /// should be stored in the 3 LSB of the word. + /// should be stored in the 3 LSB of the word. Note that if amplitude scaling is to be used, + /// the "Amplitude multiplier enable" bit must be set. pub fn update_channels( &mut self, channels: &[Channel],