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Merge pull request #330 from quartiq/rs/issue-264/pounder-acr-write 

Fixing ACR write padding
master
Ryan Summers 2021-04-08 16:09:46 +02:00 committed by GitHub
parent c1f256ea77 090ec4650d
commit dfd1a008bd
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 11 additions and 8 deletions
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14
ad9959/src/lib.rs
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@ -558,13 +558,15 @@ impl ProfileSerializer {
/// * `channels` - A list of channels to apply the configuration to.
/// * `ftw` - If provided, indicates a frequency tuning word for the channels.
/// * `pow` - If provided, indicates a phase offset word for the channels.
/// * `acr` - If provided, indicates the amplitude control register for the channels.
/// * `acr` - If provided, indicates the amplitude control register for the channels. The ACR
/// should be stored in the 3 LSB of the word. Note that if amplitude scaling is to be used,
/// the "Amplitude multiplier enable" bit must be set.
pub fn update_channels(
&mut self,
channels: &[Channel],
ftw: Option<u32>,
pow: Option<u16>,
acr: Option<u16>,
acr: Option<u32>,
) {
let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8);
for channel in channels.iter() {
@ -582,7 +584,7 @@ impl ProfileSerializer {
}
if let Some(acr) = acr {
self.add_write(Register::ACR, &acr.to_be_bytes());
self.add_write(Register::ACR, &acr.to_be_bytes()[1..=3]);
}
}
@ -606,14 +608,14 @@ impl ProfileSerializer {
// Pad the buffer to 32-bit alignment by adding dummy writes to CSR and LSRR.
let padding = 4 - (self.index % 4);
match padding {
0 => {}
1 => {
// For a pad size of 1, we have to pad with 5 bytes to align things.
self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
self.add_write(Register::LSRR, &[0, 0, 0]);
self.add_write(Register::LSRR, &[0, 0]);
}
2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]),
3 => self.add_write(Register::LSRR, &[0, 0, 0]),
3 => self.add_write(Register::LSRR, &[0, 0]),
4 => {}
_ => unreachable!(),
}

5
src/hardware/pounder/dds_output.rs
View File

@ -144,14 +144,15 @@ impl<'a> ProfileBuilder<'a> {
/// * `channels` - A list of channels to apply the configuration to.
/// * `ftw` - If provided, indicates a frequency tuning word for the channels.
/// * `pow` - If provided, indicates a phase offset word for the channels.
/// * `acr` - If provided, indicates the amplitude control register for the channels.
/// * `acr` - If provided, indicates the amplitude control register for the channels. The
/// 24-bits of the ACR should be stored in the last 3 LSB.
#[allow(dead_code)]
pub fn update_channels(
mut self,
channels: &[Channel],
ftw: Option<u32>,
pow: Option<u16>,
acr: Option<u16>,
acr: Option<u32>,
) -> Self {
self.serializer.update_channels(channels, ftw, pow, acr);
self