WIP updates
This commit is contained in:
parent
66c917b576
commit
dac6f73d5e
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@ -310,9 +310,9 @@ dependencies = [
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[[package]]
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name = "paste"
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version = "0.1.17"
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version = "0.1.18"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "026c63fe245362be0322bfec5a9656d458d13f9cfb1785d1b38458b9968e8080"
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checksum = "45ca20c77d80be666aef2b45486da86238fabe33e38306bd3118fe4af33fa880"
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dependencies = [
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"paste-impl",
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"proc-macro-hack",
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@ -320,9 +320,9 @@ dependencies = [
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[[package]]
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name = "paste-impl"
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version = "0.1.17"
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version = "0.1.18"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "7b9281a268ec213237dcd2aa3c3d0f46681b04ced37c1616fd36567a9e6954b0"
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checksum = "d95a7db200b97ef370c8e6de0088252f7e0dfff7d047a28528e47456c0fc98b6"
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dependencies = [
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"proc-macro-hack",
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]
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@ -462,7 +462,7 @@ dependencies = [
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"serde-json-core",
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"smoltcp",
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"stm32h7-ethernet",
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"stm32h7xx-hal 0.5.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support)",
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"stm32h7xx-hal 0.7.1",
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]
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[[package]]
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@ -491,23 +491,7 @@ dependencies = [
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"cortex-m",
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"log",
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"smoltcp",
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"stm32h7xx-hal 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "stm32h7xx-hal"
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version = "0.5.0"
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source = "git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support#ff00e938f2b226211c178f26c092f36462c44404"
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dependencies = [
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"bare-metal",
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"cast",
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"cortex-m",
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"cortex-m-rt",
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"embedded-hal",
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"nb 0.1.2",
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"paste",
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"stm32h7",
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"void",
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"stm32h7xx-hal 0.5.0",
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]
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[[package]]
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@ -527,6 +511,22 @@ dependencies = [
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"void",
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]
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[[package]]
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name = "stm32h7xx-hal"
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version = "0.7.1"
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dependencies = [
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"bare-metal",
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"cast",
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"cortex-m",
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"cortex-m-rt",
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"embedded-hal",
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"nb 0.1.2",
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"paste",
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"smoltcp",
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"stm32h7",
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"void",
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]
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[[package]]
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name = "syn"
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version = "1.0.33"
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@ -58,10 +58,8 @@ branch = "master"
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features = ["stm32h743v"]
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[dependencies.stm32h7xx-hal]
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features = ["stm32h743v", "rt", "unproven"]
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[patch.crates-io]
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stm32h7xx-hal = { git = "https://github.com/quartiq/stm32h7xx-hal.git", branch = "feature/pounder-support" }
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features = ["stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a", "quadspi"]
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path = "../stm32h7xx-hal"
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[features]
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semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
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@ -571,4 +571,48 @@ where
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Ok(tuning_word as f64 * self.system_clock_frequency()
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/ (1u64 << 32) as f64)
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}
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pub fn write_profile(&mut self, channel: Channel, freq: f64, turns: f32) -> Result<(), Error> {
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// The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the
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// frequency tuning word and f_s is the system clock rate.
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let tuning_word: u32 =
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((freq as f64 / self.system_clock_frequency())
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* 1u64.wrapping_shl(32) as f64) as u32;
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let phase_offset: u16 = (turns * (1 << 14) as f32) as u16 & 0x3FFFu16;
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self.modify_channel_closure(channel, |interface| {
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let mut data: [u8; 7] = [0; 7];
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data[0..2].copy_from_slice(&phase_offset.to_be_bytes());
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data[3] = Register::CFTW0 as u8;
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data[4..7].copy_from_slice(&tuning_word.to_be_bytes());
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interface.write(Register::CPOW0 as u8, &data).map_err(|_| Error::Interface)
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})?;
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Ok(())
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}
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fn modify_channel_closure<F>(&mut self, channel: Channel, f: F) -> Result<(), Error>
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where
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F: FnOnce(&mut INTERFACE) -> Result<(), Error>,
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{
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// Disable all other outputs so that we can update the configuration register of only the
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// specified channel.
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let mut csr: [u8; 1] = [0];
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self.interface
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.read(Register::CSR as u8, &mut csr)
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.map_err(|_| Error::Interface)?;
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let mut new_csr = csr;
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new_csr[0].set_bits(4..8, 0);
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new_csr[0].set_bit(4 + channel as usize, true);
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let result = f(&mut self.interface);
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self.interface
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.write(Register::CSR as u8, &new_csr)
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.map_err(|_| Error::Interface)?;
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result
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}
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}
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140
src/main.rs
140
src/main.rs
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@ -36,7 +36,7 @@ use stm32h7xx_hal::prelude::*;
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use smoltcp as net;
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use stm32h7_ethernet as ethernet;
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use hal::ethernet as ethernet;
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use heapless::{consts::*, String};
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@ -160,12 +160,12 @@ macro_rules! route_request {
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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adc0: hal::spi::Spi<hal::stm32::SPI2>,
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dac0: hal::spi::Spi<hal::stm32::SPI4>,
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adc0: hal::spi::Spi<hal::stm32::SPI2, hal::spi::Enabled, u16>,
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dac0: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
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afe0: AFE0,
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adc1: hal::spi::Spi<hal::stm32::SPI3>,
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dac1: hal::spi::Spi<hal::stm32::SPI5>,
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adc1: hal::spi::Spi<hal::stm32::SPI3, hal::spi::Enabled, u16>,
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dac1: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
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afe1: AFE1,
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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@ -208,8 +208,19 @@ const APP: () = {
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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// Enable SRAM3 for the ethernet descriptor ring.
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dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Clear reset flags.
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dp.RCC.rsr.write(|w| w.rmvf().set_bit());
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// Select the PLLs for SPI.
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dp.RCC
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.d2ccip1r
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.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let rcc = dp.RCC.constrain();
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let mut clocks = rcc
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let clocks = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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@ -220,25 +231,15 @@ const APP: () = {
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init_log();
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// Enable SRAM3 for the ethernet descriptor ring.
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clocks.rb.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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clocks.rb.rsr.write(|w| w.rmvf().set_bit());
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clocks
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.rb
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.d2ccip1r
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.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks);
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let gpioa = dp.GPIOA.split(&mut clocks);
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let gpiob = dp.GPIOB.split(&mut clocks);
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let gpioc = dp.GPIOC.split(&mut clocks);
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let gpiod = dp.GPIOD.split(&mut clocks);
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let gpioe = dp.GPIOE.split(&mut clocks);
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let gpiof = dp.GPIOF.split(&mut clocks);
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let gpiog = dp.GPIOG.split(&mut clocks);
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let gpioa = dp.GPIOA.split(clocks.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(clocks.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(clocks.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(clocks.peripheral.GPIOD);
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let gpioe = dp.GPIOE.split(clocks.peripheral.GPIOE);
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let gpiof = dp.GPIOF.split(clocks.peripheral.GPIOF);
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let gpiog = dp.GPIOG.split(clocks.peripheral.GPIOG);
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let afe0 = {
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let a0_pin = gpiof.pf2.into_push_pull_output();
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@ -274,14 +275,14 @@ const APP: () = {
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.communication_mode(hal::spi::CommunicationMode::Receiver)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.cs_delay(220e-9);
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let mut spi = dp.SPI2.spi(
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let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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&clocks,
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clocks.peripheral.SPI2,
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&clocks.clocks,
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);
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spi.listen(hal::spi::Event::Eot);
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@ -310,14 +311,14 @@ const APP: () = {
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.communication_mode(hal::spi::CommunicationMode::Receiver)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.cs_delay(220e-9);
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let mut spi = dp.SPI3.spi(
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let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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&clocks,
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clocks.peripheral.SPI3,
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&clocks.clocks,
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);
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spi.listen(hal::spi::Event::Eot);
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@ -352,14 +353,14 @@ const APP: () = {
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.swap_mosi_miso();
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dp.SPI4.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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&clocks,
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clocks.peripheral.SPI4,
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&clocks.clocks,
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)
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};
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@ -384,14 +385,14 @@ const APP: () = {
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.swap_mosi_miso();
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dp.SPI5.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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&clocks,
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clocks.peripheral.SPI5,
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&clocks.clocks,
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)
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};
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@ -412,36 +413,39 @@ const APP: () = {
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let ad9959 = {
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let qspi_interface = {
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// Instantiate the QUADSPI pins and peripheral interface.
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// TODO: Place these into a pins structure that is provided to the QSPI
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// constructor.
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let _qspi_clk = gpiob
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.pb2
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.into_alternate_af9()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let qspi_pins = {
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let _qspi_ncs = gpioc
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.pc11
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.into_alternate_af9()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _qspi_io0 = gpioe
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let clk = gpiob
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.pb2
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.into_alternate_af9()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let io0 = gpioe
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.pe7
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _qspi_io1 = gpioe
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let io1 = gpioe
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.pe8
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _qspi_io2 = gpioe
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let io2 = gpioe
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.pe9
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _qspi_io3 = gpioe
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let io3 = gpioe
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.pe10
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let qspi =
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hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz())
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.unwrap();
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(clk, io0, io1, io2, io3)
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};
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let qspi = hal::qspi::Qspi::bank2(dp.QUADSPI, qspi_pins, 11.mhz(), &clocks.clocks,
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clocks.peripheral.QSPI);
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pounder::QspiInterface::new(qspi).unwrap()
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};
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@ -470,7 +474,7 @@ const APP: () = {
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let io_expander = {
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let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
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let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks);
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let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C1, &clocks.clocks);
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mcp23017::MCP23017::default(i2c1).unwrap()
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};
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@ -491,8 +495,7 @@ const APP: () = {
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.frame_size(8);
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});
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// The maximum frequency of this SPI must be limited due to capacitance on the MISO
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// line causing a long RC decay.
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@ -500,22 +503,25 @@ const APP: () = {
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(spi_sck, spi_miso, spi_mosi),
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config,
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5.mhz(),
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&clocks,
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clocks.peripheral.SPI1,
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&clocks.clocks,
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)
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};
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let adc1 = {
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let mut adc = dp.ADC1.adc(&mut delay, &mut clocks);
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adc.calibrate();
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let (adc1, adc2) = {
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let (mut adc1, mut adc2) = hal::adc::adc12(dp.ADC1, dp.ADC2, &mut delay, clocks.peripheral.ADC12, &clocks.clocks);
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adc.enable()
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let adc1 = {
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adc1.calibrate();
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adc1.enable()
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};
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let adc2 = {
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let mut adc = dp.ADC2.adc(&mut delay, &mut clocks);
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adc.calibrate();
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adc2.calibrate();
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adc2.enable()
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};
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adc.enable()
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(adc1, adc2)
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};
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let adc1_in_p = gpiof.pf11.into_analog();
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@ -540,16 +546,16 @@ const APP: () = {
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let mut eeprom_i2c = {
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let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
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let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
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dp.I2C2.i2c((scl, sda), 100.khz(), &clocks)
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dp.I2C2.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C2, &clocks.clocks)
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};
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// Configure ethernet pins.
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{
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// Reset the PHY before configuring pins.
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let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
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eth_phy_nrst.set_low().unwrap();
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delay.delay_us(200u8);
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eth_phy_nrst.set_high().unwrap();
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//let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
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//eth_phy_nrst.set_low().unwrap();
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//delay.delay_ms(200u8);
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//eth_phy_nrst.set_high().unwrap();
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let _rmii_ref_clk = gpioa
|
||||
.pa1
|
||||
.into_alternate_af11()
|
||||
|
|
@ -598,8 +604,8 @@ const APP: () = {
|
|||
|
||||
let (network_interface, eth_mac) = {
|
||||
// Configure the ethernet controller
|
||||
let (eth_dma, eth_mac) = unsafe {
|
||||
ethernet::ethernet_init(
|
||||
let (eth_dma, mut eth_mac) = unsafe {
|
||||
ethernet::new_unchecked(
|
||||
dp.ETHERNET_MAC,
|
||||
dp.ETHERNET_MTL,
|
||||
dp.ETHERNET_DMA,
|
||||
|
|
@ -608,6 +614,8 @@ const APP: () = {
|
|||
)
|
||||
};
|
||||
|
||||
eth_mac.block_until_link();
|
||||
|
||||
unsafe { ethernet::enable_interrupt() };
|
||||
|
||||
let store = unsafe { &mut NET_STORE };
|
||||
|
|
@ -638,7 +646,7 @@ const APP: () = {
|
|||
// Utilize the cycle counter for RTIC scheduling.
|
||||
cp.DWT.enable_cycle_counter();
|
||||
|
||||
let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks);
|
||||
let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, clocks.peripheral.DMA1);
|
||||
dma.configure_m2p_stream(
|
||||
hal::dma::Stream::One,
|
||||
&SPI_START_CODE as *const _ as u32,
|
||||
|
|
@ -654,7 +662,7 @@ const APP: () = {
|
|||
);
|
||||
|
||||
// Configure timer 2 to trigger conversions for the ADC
|
||||
let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks);
|
||||
let mut timer2 = dp.TIM2.timer(50.khz(), clocks.peripheral.TIM2, &clocks.clocks);
|
||||
timer2.configure_channel(hal::timer::Channel::One, 0.25);
|
||||
timer2.configure_channel(hal::timer::Channel::Two, 0.75);
|
||||
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ pub struct PounderDevices<DELAY> {
|
|||
hal::gpio::gpiog::PG7<hal::gpio::Output<hal::gpio::PushPull>>,
|
||||
>,
|
||||
mcp23017: mcp23017::MCP23017<hal::i2c::I2c<hal::stm32::I2C1>>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1, hal::spi::Enabled, u8>,
|
||||
adc1: hal::adc::Adc<hal::stm32::ADC1, hal::adc::Enabled>,
|
||||
adc2: hal::adc::Adc<hal::stm32::ADC2, hal::adc::Enabled>,
|
||||
adc1_in_p: hal::gpio::gpiof::PF11<hal::gpio::Analog>,
|
||||
|
|
@ -262,7 +262,7 @@ where
|
|||
DELAY,
|
||||
hal::gpio::gpiog::PG7<hal::gpio::Output<hal::gpio::PushPull>>,
|
||||
>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1, hal::spi::Enabled, u8>,
|
||||
adc1: hal::adc::Adc<hal::stm32::ADC1, hal::adc::Enabled>,
|
||||
adc2: hal::adc::Adc<hal::stm32::ADC2, hal::adc::Enabled>,
|
||||
adc1_in_p: hal::gpio::gpiof::PF11<hal::gpio::Analog>,
|
||||
|
|
@ -474,12 +474,8 @@ where
|
|||
channel: Channel,
|
||||
state: ChannelState,
|
||||
) -> Result<(), Error> {
|
||||
self.ad9959
|
||||
.set_frequency(channel.into(), state.parameters.frequency)
|
||||
.map_err(|_| Error::Dds)?;
|
||||
self.ad9959
|
||||
.set_phase(channel.into(), state.parameters.phase_offset)
|
||||
.map_err(|_| Error::Dds)?;
|
||||
self.ad9959.write_profile(channel.into(), state.parameters.frequency,
|
||||
state.parameters.phase_offset).map_err(|_| Error::Dds)?;
|
||||
self.ad9959
|
||||
.set_amplitude(channel.into(), state.parameters.amplitude)
|
||||
.map_err(|_| Error::Dds)?;
|
||||
|
|
|
|||
Loading…
Reference in New Issue