diff --git a/Cargo.lock b/Cargo.lock index 082a02c..3d3e736 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -310,9 +310,9 @@ dependencies = [ [[package]] name = "paste" -version = "0.1.17" +version = "0.1.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "026c63fe245362be0322bfec5a9656d458d13f9cfb1785d1b38458b9968e8080" +checksum = "45ca20c77d80be666aef2b45486da86238fabe33e38306bd3118fe4af33fa880" dependencies = [ "paste-impl", "proc-macro-hack", @@ -320,9 +320,9 @@ dependencies = [ [[package]] name = "paste-impl" -version = "0.1.17" +version = "0.1.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7b9281a268ec213237dcd2aa3c3d0f46681b04ced37c1616fd36567a9e6954b0" +checksum = "d95a7db200b97ef370c8e6de0088252f7e0dfff7d047a28528e47456c0fc98b6" dependencies = [ "proc-macro-hack", ] @@ -462,7 +462,7 @@ dependencies = [ "serde-json-core", "smoltcp", "stm32h7-ethernet", - "stm32h7xx-hal 0.5.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support)", + "stm32h7xx-hal 0.7.1", ] [[package]] @@ -491,23 +491,7 @@ dependencies = [ "cortex-m", "log", "smoltcp", - "stm32h7xx-hal 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - -[[package]] -name = "stm32h7xx-hal" -version = "0.5.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support#ff00e938f2b226211c178f26c092f36462c44404" -dependencies = [ - "bare-metal", - "cast", - "cortex-m", - "cortex-m-rt", - "embedded-hal", - "nb 0.1.2", - "paste", - "stm32h7", - "void", + "stm32h7xx-hal 0.5.0", ] [[package]] @@ -527,6 +511,22 @@ dependencies = [ "void", ] +[[package]] +name = "stm32h7xx-hal" +version = "0.7.1" +dependencies = [ + "bare-metal", + "cast", + "cortex-m", + "cortex-m-rt", + "embedded-hal", + "nb 0.1.2", + "paste", + "smoltcp", + "stm32h7", + "void", +] + [[package]] name = "syn" version = "1.0.33" diff --git a/Cargo.toml b/Cargo.toml index 0595c33..519fc08 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -58,10 +58,8 @@ branch = "master" features = ["stm32h743v"] [dependencies.stm32h7xx-hal] -features = ["stm32h743v", "rt", "unproven"] - -[patch.crates-io] -stm32h7xx-hal = { git = "https://github.com/quartiq/stm32h7xx-hal.git", branch = "feature/pounder-support" } +features = ["stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a", "quadspi"] +path = "../stm32h7xx-hal" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index d12041c..a3d42bf 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -571,4 +571,48 @@ where Ok(tuning_word as f64 * self.system_clock_frequency() / (1u64 << 32) as f64) } + + pub fn write_profile(&mut self, channel: Channel, freq: f64, turns: f32) -> Result<(), Error> { + // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the + // frequency tuning word and f_s is the system clock rate. + let tuning_word: u32 = + ((freq as f64 / self.system_clock_frequency()) + * 1u64.wrapping_shl(32) as f64) as u32; + + let phase_offset: u16 = (turns * (1 << 14) as f32) as u16 & 0x3FFFu16; + + self.modify_channel_closure(channel, |interface| { + let mut data: [u8; 7] = [0; 7]; + data[0..2].copy_from_slice(&phase_offset.to_be_bytes()); + data[3] = Register::CFTW0 as u8; + data[4..7].copy_from_slice(&tuning_word.to_be_bytes()); + interface.write(Register::CPOW0 as u8, &data).map_err(|_| Error::Interface) + })?; + + Ok(()) + } + + fn modify_channel_closure(&mut self, channel: Channel, f: F) -> Result<(), Error> + where + F: FnOnce(&mut INTERFACE) -> Result<(), Error>, + { + // Disable all other outputs so that we can update the configuration register of only the + // specified channel. + let mut csr: [u8; 1] = [0]; + self.interface + .read(Register::CSR as u8, &mut csr) + .map_err(|_| Error::Interface)?; + + let mut new_csr = csr; + new_csr[0].set_bits(4..8, 0); + new_csr[0].set_bit(4 + channel as usize, true); + + let result = f(&mut self.interface); + + self.interface + .write(Register::CSR as u8, &new_csr) + .map_err(|_| Error::Interface)?; + + result + } } diff --git a/src/main.rs b/src/main.rs index 9e0c0ff..9be0830 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,7 +36,7 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; use smoltcp as net; -use stm32h7_ethernet as ethernet; +use hal::ethernet as ethernet; use heapless::{consts::*, String}; @@ -160,12 +160,12 @@ macro_rules! route_request { #[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { - adc0: hal::spi::Spi, - dac0: hal::spi::Spi, + adc0: hal::spi::Spi, + dac0: hal::spi::Spi, afe0: AFE0, - adc1: hal::spi::Spi, - dac1: hal::spi::Spi, + adc1: hal::spi::Spi, + dac1: hal::spi::Spi, afe1: AFE1, eeprom_i2c: hal::i2c::I2c, @@ -208,8 +208,19 @@ const APP: () = { let pwr = dp.PWR.constrain(); let vos = pwr.freeze(); + // Enable SRAM3 for the ethernet descriptor ring. + dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + + // Clear reset flags. + dp.RCC.rsr.write(|w| w.rmvf().set_bit()); + + // Select the PLLs for SPI. + dp.RCC + .d2ccip1r + .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); + let rcc = dp.RCC.constrain(); - let mut clocks = rcc + let clocks = rcc .use_hse(8.mhz()) .sysclk(400.mhz()) .hclk(200.mhz()) @@ -220,25 +231,15 @@ const APP: () = { init_log(); - // Enable SRAM3 for the ethernet descriptor ring. - clocks.rb.ahb2enr.modify(|_, w| w.sram3en().set_bit()); - - clocks.rb.rsr.write(|w| w.rmvf().set_bit()); - - clocks - .rb - .d2ccip1r - .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); - let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks); - let gpioa = dp.GPIOA.split(&mut clocks); - let gpiob = dp.GPIOB.split(&mut clocks); - let gpioc = dp.GPIOC.split(&mut clocks); - let gpiod = dp.GPIOD.split(&mut clocks); - let gpioe = dp.GPIOE.split(&mut clocks); - let gpiof = dp.GPIOF.split(&mut clocks); - let gpiog = dp.GPIOG.split(&mut clocks); + let gpioa = dp.GPIOA.split(clocks.peripheral.GPIOA); + let gpiob = dp.GPIOB.split(clocks.peripheral.GPIOB); + let gpioc = dp.GPIOC.split(clocks.peripheral.GPIOC); + let gpiod = dp.GPIOD.split(clocks.peripheral.GPIOD); + let gpioe = dp.GPIOE.split(clocks.peripheral.GPIOE); + let gpiof = dp.GPIOF.split(clocks.peripheral.GPIOF); + let gpiog = dp.GPIOG.split(clocks.peripheral.GPIOG); let afe0 = { let a0_pin = gpiof.pf2.into_push_pull_output(); @@ -274,14 +275,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() .transfer_size(1) - .frame_size(16) .cs_delay(220e-9); - let mut spi = dp.SPI2.spi( + let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI2, + &clocks.clocks, ); spi.listen(hal::spi::Event::Eot); @@ -310,14 +311,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() .transfer_size(1) - .frame_size(16) .cs_delay(220e-9); - let mut spi = dp.SPI3.spi( + let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI3, + &clocks.clocks, ); spi.listen(hal::spi::Event::Eot); @@ -352,14 +353,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() .transfer_size(1) - .frame_size(16) .swap_mosi_miso(); dp.SPI4.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI4, + &clocks.clocks, ) }; @@ -384,14 +385,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() .transfer_size(1) - .frame_size(16) .swap_mosi_miso(); dp.SPI5.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI5, + &clocks.clocks, ) }; @@ -412,36 +413,39 @@ const APP: () = { let ad9959 = { let qspi_interface = { // Instantiate the QUADSPI pins and peripheral interface. - // TODO: Place these into a pins structure that is provided to the QSPI - // constructor. - let _qspi_clk = gpiob - .pb2 - .into_alternate_af9() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_ncs = gpioc - .pc11 - .into_alternate_af9() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io0 = gpioe - .pe7 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io1 = gpioe - .pe8 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io2 = gpioe - .pe9 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io3 = gpioe - .pe10 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); + let qspi_pins = { - let qspi = - hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()) - .unwrap(); + let _qspi_ncs = gpioc + .pc11 + .into_alternate_af9() + .set_speed(hal::gpio::Speed::VeryHigh); + + let clk = gpiob + .pb2 + .into_alternate_af9() + .set_speed(hal::gpio::Speed::VeryHigh); + let io0 = gpioe + .pe7 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io1 = gpioe + .pe8 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io2 = gpioe + .pe9 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io3 = gpioe + .pe10 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + + (clk, io0, io1, io2, io3) + }; + + let qspi = hal::qspi::Qspi::bank2(dp.QUADSPI, qspi_pins, 11.mhz(), &clocks.clocks, + clocks.peripheral.QSPI); pounder::QspiInterface::new(qspi).unwrap() }; @@ -470,7 +474,7 @@ const APP: () = { let io_expander = { let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); - let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks); + let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C1, &clocks.clocks); mcp23017::MCP23017::default(i2c1).unwrap() }; @@ -491,8 +495,7 @@ const APP: () = { let config = hal::spi::Config::new(hal::spi::Mode { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .frame_size(8); + }); // The maximum frequency of this SPI must be limited due to capacitance on the MISO // line causing a long RC decay. @@ -500,22 +503,25 @@ const APP: () = { (spi_sck, spi_miso, spi_mosi), config, 5.mhz(), - &clocks, + clocks.peripheral.SPI1, + &clocks.clocks, ) }; - let adc1 = { - let mut adc = dp.ADC1.adc(&mut delay, &mut clocks); - adc.calibrate(); + let (adc1, adc2) = { + let (mut adc1, mut adc2) = hal::adc::adc12(dp.ADC1, dp.ADC2, &mut delay, clocks.peripheral.ADC12, &clocks.clocks); - adc.enable() - }; + let adc1 = { + adc1.calibrate(); + adc1.enable() + }; - let adc2 = { - let mut adc = dp.ADC2.adc(&mut delay, &mut clocks); - adc.calibrate(); + let adc2 = { + adc2.calibrate(); + adc2.enable() + }; - adc.enable() + (adc1, adc2) }; let adc1_in_p = gpiof.pf11.into_analog(); @@ -540,16 +546,16 @@ const APP: () = { let mut eeprom_i2c = { let sda = gpiof.pf0.into_alternate_af4().set_open_drain(); let scl = gpiof.pf1.into_alternate_af4().set_open_drain(); - dp.I2C2.i2c((scl, sda), 100.khz(), &clocks) + dp.I2C2.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C2, &clocks.clocks) }; // Configure ethernet pins. { // Reset the PHY before configuring pins. - let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output(); - eth_phy_nrst.set_low().unwrap(); - delay.delay_us(200u8); - eth_phy_nrst.set_high().unwrap(); + //let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output(); + //eth_phy_nrst.set_low().unwrap(); + //delay.delay_ms(200u8); + //eth_phy_nrst.set_high().unwrap(); let _rmii_ref_clk = gpioa .pa1 .into_alternate_af11() @@ -598,8 +604,8 @@ const APP: () = { let (network_interface, eth_mac) = { // Configure the ethernet controller - let (eth_dma, eth_mac) = unsafe { - ethernet::ethernet_init( + let (eth_dma, mut eth_mac) = unsafe { + ethernet::new_unchecked( dp.ETHERNET_MAC, dp.ETHERNET_MTL, dp.ETHERNET_DMA, @@ -608,6 +614,8 @@ const APP: () = { ) }; + eth_mac.block_until_link(); + unsafe { ethernet::enable_interrupt() }; let store = unsafe { &mut NET_STORE }; @@ -638,7 +646,7 @@ const APP: () = { // Utilize the cycle counter for RTIC scheduling. cp.DWT.enable_cycle_counter(); - let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks); + let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, clocks.peripheral.DMA1); dma.configure_m2p_stream( hal::dma::Stream::One, &SPI_START_CODE as *const _ as u32, @@ -654,7 +662,7 @@ const APP: () = { ); // Configure timer 2 to trigger conversions for the ADC - let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks); + let mut timer2 = dp.TIM2.timer(50.khz(), clocks.peripheral.TIM2, &clocks.clocks); timer2.configure_channel(hal::timer::Channel::One, 0.25); timer2.configure_channel(hal::timer::Channel::Two, 0.75); diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 1288765..489cc67 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -235,7 +235,7 @@ pub struct PounderDevices { hal::gpio::gpiog::PG7>, >, mcp23017: mcp23017::MCP23017>, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -262,7 +262,7 @@ where DELAY, hal::gpio::gpiog::PG7>, >, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -474,12 +474,8 @@ where channel: Channel, state: ChannelState, ) -> Result<(), Error> { - self.ad9959 - .set_frequency(channel.into(), state.parameters.frequency) - .map_err(|_| Error::Dds)?; - self.ad9959 - .set_phase(channel.into(), state.parameters.phase_offset) - .map_err(|_| Error::Dds)?; + self.ad9959.write_profile(channel.into(), state.parameters.frequency, + state.parameters.phase_offset).map_err(|_| Error::Dds)?; self.ad9959 .set_amplitude(channel.into(), state.parameters.amplitude) .map_err(|_| Error::Dds)?;