Adding WIP updates to HAL API
This commit is contained in:
parent
820a37a625
commit
d700935246
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@ -2,6 +2,7 @@ use embedded_hal::blocking::i2c::WriteRead;
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const I2C_ADDR: u8 = 0x50;
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#[allow(dead_code)]
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pub fn read_eui48<T>(i2c: &mut T) -> Result<[u8; 6], T::Error>
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where T: WriteRead
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{
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251
src/main.rs
251
src/main.rs
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@ -28,10 +28,8 @@ extern crate panic_halt;
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extern crate log;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use core::fmt::Write;
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use cortex_m_rt::exception;
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use heapless::{consts::*, String, Vec};
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use rtfm::cyccnt::{Instant, U32Ext as _};
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use rtfm::cyccnt::{U32Ext as _};
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::{
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prelude::*,
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@ -42,10 +40,13 @@ use embedded_hal::{
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digital::v2::OutputPin,
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};
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/*
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use core::fmt::Write;
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use heapless::{consts::*, String, Vec};
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use smoltcp as net;
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use serde::{de::DeserializeOwned, Deserialize, Serialize};
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use serde_json_core::{de::from_slice, ser::to_string};
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*/
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mod eth;
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@ -83,6 +84,7 @@ const SCALE: f32 = ((1 << 15) - 1) as f32;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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/*
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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@ -99,79 +101,32 @@ macro_rules! create_socket {
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let $target = $set.add(tcp_socket);
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};
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}
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type Adc1Spi = hal::spi::Spi<
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hal::stm32::SPI2,
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(
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hal::gpio::gpiob::PB10<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::gpio::gpiob::PB14<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::spi::NoMosi,
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//hal::gpio::gpiob::PB9<hal::gpio::Alternate<hal::gpio::AF5>>,
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)
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>;
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type Adc2Spi = hal::spi::Spi<
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hal::stm32::SPI3,
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(
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hal::gpio::gpioc::PC10<hal::gpio::Alternate<hal::gpio::AF6>>,
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hal::gpio::gpiob::PB4<hal::gpio::Alternate<hal::gpio::AF6>>,
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hal::spi::NoMosi,
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//hal::gpio::gpioa::PA15<hal::gpio::Alternate<hal::gpio::AF6>>,
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)
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>;
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type Dac1Spi = hal::spi::Spi<
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hal::stm32::SPI4,
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(
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hal::gpio::gpioe::PE2<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::gpio::gpioe::PE5<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::spi::NoMosi,
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//hal::gpio::gpioe::PE4<hal::gpio::Alternate<hal::gpio::AF5>>,
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)
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>;
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type Dac2Spi = hal::spi::Spi<
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hal::stm32::SPI5,
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(
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hal::gpio::gpiof::PF7<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::gpio::gpiof::PF8<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::spi::NoMosi,
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//hal::gpio::gpiof::PF6<hal::gpio::Alternate<hal::gpio::AF5>>,
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)
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>;
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type EepromI2c = hal::i2c::I2c<
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hal::stm32::I2C2,
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(
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hal::gpio::gpiof::PF1<hal::gpio::Alternate<hal::gpio::AF4>>,
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hal::gpio::gpiof::PF0<hal::gpio::Alternate<hal::gpio::AF4>>,
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)
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>;
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*/
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static DAT: u32 = 0x30; // EN | CSTART
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#[rtfm::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtfm::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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adc1: Adc1Spi,
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dac1: Dac1Spi,
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adc1: hal::spi::Spi<hal::stm32::SPI2>,
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dac1: hal::spi::Spi<hal::stm32::SPI4>,
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adc2: Adc2Spi,
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dac2: Dac2Spi,
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adc2: hal::spi::Spi<hal::stm32::SPI3>,
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dac2: hal::spi::Spi<hal::stm32::SPI5>,
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i2c: EepromI2c,
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_eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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// TODO: Add in pounder hardware resources.
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ethernet_periph:
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(pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL),
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//ethernet_periph:
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// (pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL),
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#[init([[0.; 5]; 2])]
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iir_state: [IIRState; 2],
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#[init([IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
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iir_ch: [IIR; 2],
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#[link_section = ".sram3.eth"]
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#[init(eth::Device::new())]
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ethernet: eth::Device,
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//#[link_section = ".sram3.eth"]
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//#[init(eth::Device::new())]
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//ethernet: eth::Device,
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}
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#[init(schedule = [tick])]
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@ -184,7 +139,7 @@ const APP: () = {
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let rcc = dp.RCC.constrain();
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let mut clocks = rcc
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.use_hse(8.mhz())
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// .use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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@ -192,6 +147,8 @@ const APP: () = {
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.pll2_q_ck(100.mhz())
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.freeze(vos, &dp.SYSCFG);
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clocks.rb.rsr.write(|w| w.rmvf().set_bit());
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clocks.rb.d2ccip1r.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let gpioa = dp.GPIOA.split(&mut clocks.ahb4);
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@ -203,54 +160,61 @@ const APP: () = {
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let gpiog = dp.GPIOG.split(&mut clocks.ahb4);
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// Configure the SPI interfaces to the ADCs and DACs.
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let adc1_spi = {
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let (adc1_spi, adc1_cr_address) = {
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let spi_miso = gpiob.pb14.into_alternate_af5();
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let spi_sck = gpiob.pb10.into_alternate_af5();
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let _spi_nss = gpiob.pb9.into_alternate_af5();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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let _config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.cs_delay(220e-9)
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.frame_size(16)
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.freeze();
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.frame_size(16);
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let spi = hal::spi::Spi::spi2(
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dp.SPI2,
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let cr_address = &dp.SPI2.cr1 as *const _ as usize;
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let mut spi = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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hal::spi::MODE_0, //config,
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25.mhz(),
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&clocks);
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//spi.listen(hal::spi::Event::Rxp);
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spi.listen(hal::spi::Event::Rxp);
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spi
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(spi, cr_address)
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};
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let adc2_spi = {
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let (adc2_spi, adc2_cr_address) = {
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let spi_miso = gpiob.pb4.into_alternate_af6();
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let spi_sck = gpioc.pc10.into_alternate_af6();
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let _spi_nss = gpioa.pa15.into_alternate_af6();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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let mut cs = gpioa.pa15.into_push_pull_output();
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cs.set_high().unwrap();
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let _spi_nss = cs.into_alternate_af6();
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.frame_size(16)
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.cs_delay(220e-9)
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.freeze();
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.cs_delay(220e-9);
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let spi = hal::spi::Spi::spi3(
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dp.SPI3,
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let cr_address = &dp.SPI3.cr1 as *const _ as usize;
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let mut spi = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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//spi.listen(hal::spi::Event::Rxp);
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spi.send(8_u8).unwrap();
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spi
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spi.listen(hal::spi::Event::Rxp);
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(spi, cr_address)
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};
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let dac1_spi = {
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@ -258,22 +222,15 @@ const APP: () = {
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let spi_sck = gpioe.pe2.into_alternate_af5();
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let _spi_nss = gpioe.pe4.into_alternate_af5();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.frame_size(16)
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.swap_mosi_miso()
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.freeze();
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.swap_mosi_miso();
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let spi = hal::spi::Spi::spi4(
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dp.SPI4,
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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spi
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dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 25.mhz(), &clocks)
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};
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let dac2_spi = {
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@ -281,48 +238,36 @@ const APP: () = {
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let spi_sck = gpiof.pf7.into_alternate_af5();
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let _spi_nss = gpiof.pf6.into_alternate_af5();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.frame_size(16)
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.swap_mosi_miso()
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.freeze();
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.swap_mosi_miso();
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let spi = hal::spi::Spi::spi5(
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dp.SPI5,
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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spi
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dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 25.mhz(), &clocks)
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};
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// TODO: Configure the DMA
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//let mut dma = Dma::new(dp.DMA1, dp.DMAMUX1);
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//dma.configure_transfer(DmaTransfer::MemoryToPeripheral, DmaSource::Timer2, trigger_word,
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// &adc1_spi.spi.ptr().cr1.register)
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//dma.configure_transfer(DmaTransfer::MemoryToPeripheral, DmaSource::Timer2, trigger_word,
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// &adc2_spi.spi.ptr().cr1.register)
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// TODO: Configure timer 2 to trigger conversions for the ADC
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let _timer2 = hal::timer::Timer::tim2(dp.TIM2, 500.khz(), &mut clocks);
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// Configure timer 2 to trigger conversions for the ADC
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let mut timer2 = hal::timer::Timer::tim2(dp.TIM2, 500.khz(), &mut clocks);
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//timer2.listen(hal::timer::Event::TimeOut);
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timer2.listen(hal::timer::Event::DmaRequest);
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cortex_m::asm::dsb();
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let dat_addr = &DAT as *const _ as usize;
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cp.SCB.clean_dcache_by_address(dat_addr, 4);
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// Enable the DMA.
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// TODO: Refactor the DMA API to be a bit cleaner.
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clocks.ahb1.enr().modify(|_, w| w.dma1en().set_bit());
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board::dma1_setup(
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&dp.DMA1,
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&dp.DMAMUX1,
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dat_addr,
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&adc1_spi.spi.cr1 as *const _ as usize,
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&adc2_spi.spi.cr1 as *const _ as usize,
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adc1_cr_address,
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adc2_cr_address,
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);
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//timer2.enable_event(hal::timer::Event::DmaTransfer);
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// TODO: Configure the ethernet controller
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// Instantiate the QUADSPI pins and peripheral interface.
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@ -347,16 +292,22 @@ const APP: () = {
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let _i2c1 = {
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let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
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let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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hal::i2c::I2c::i2c1(dp.I2C1, (scl, sda), 100.khz(), &clocks)
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dp.I2C1.i2c((scl, sda), 100.khz(), &clocks)
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};
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let i2c2 = {
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let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
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let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
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hal::i2c::I2c::i2c2(dp.I2C2, (scl, sda), 100.khz(), &clocks)
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dp.I2C2.i2c((scl, sda), 100.khz(), &clocks)
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};
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// Configure ethernet pins.
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// Reset the PHY before configuring pins.
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let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
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eth_phy_nrst.set_high().unwrap();
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eth_phy_nrst.set_low().unwrap();
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eth_phy_nrst.set_high().unwrap();
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let _rmii_ref_clk = gpioa.pa1.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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@ -365,19 +316,18 @@ const APP: () = {
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let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_tx_en = gpiob.pb11.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_txd0 = gpiob.pb12.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_txd1 = gpiog.pg14.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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// TODO: This configuration seems to cause a system reset?
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//let _rmii_txd1 = gpiog.pg14.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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// TODO: Configure the ethernet controller
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// Enable the ethernet peripheral.
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clocks.apb4.enr().modify(|_, w| w.syscfgen().set_bit());
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clocks.ahb1.enr().modify(|_, w| {
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w.eth1macen().set_bit()
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.eth1txen().set_bit()
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.eth1rxen().set_bit()
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});
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//clocks.apb4.enr().modify(|_, w| w.syscfgen().set_bit());
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//clocks.ahb1.enr().modify(|_, w| {
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// w.eth1macen().set_bit()
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// .eth1txen().set_bit()
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// .eth1rxen().set_bit()
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//});
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dp.SYSCFG.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
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//dp.SYSCFG.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
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cp.SCB.enable_icache();
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@ -397,15 +347,22 @@ const APP: () = {
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adc2: adc2_spi,
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dac2: dac2_spi,
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i2c: i2c2,
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ethernet_periph: (
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dp.ETHERNET_MAC,
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dp.ETHERNET_DMA,
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dp.ETHERNET_MTL,
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),
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_eeprom_i2c: i2c2,
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// ethernet_periph: (
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// dp.ETHERNET_MAC,
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// dp.ETHERNET_DMA,
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// dp.ETHERNET_MTL,
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// ),
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}
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}
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#[idle]
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fn idle(_c: idle::Context) -> ! {
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// TODO Implement and poll ethernet interface.
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loop {}
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}
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/*
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#[idle(resources = [ethernet, ethernet_periph, iir_state, iir_ch, i2c])]
|
||||
fn idle(c: idle::Context) -> ! {
|
||||
let (MAC, DMA, MTL) = c.resources.ethernet_periph;
|
||||
|
|
@ -506,6 +463,7 @@ const APP: () = {
|
|||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
#[task(priority = 1, schedule = [tick])]
|
||||
fn tick(c: tick::Context) {
|
||||
|
|
@ -515,6 +473,11 @@ const APP: () = {
|
|||
c.schedule.tick(c.scheduled + PERIOD.cycles()).unwrap();
|
||||
}
|
||||
|
||||
#[task(binds = TIM2)]
|
||||
fn tim2(_c: tim2::Context) {
|
||||
info!("TIM2 interrupt");
|
||||
}
|
||||
|
||||
// seems to slow it down
|
||||
// #[link_section = ".data.spi1"]
|
||||
#[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
|
||||
|
|
@ -583,6 +546,7 @@ const APP: () = {
|
|||
}
|
||||
};
|
||||
|
||||
/*
|
||||
#[derive(Deserialize, Serialize)]
|
||||
struct Request {
|
||||
channel: u8,
|
||||
|
|
@ -692,6 +656,7 @@ impl Server {
|
|||
None
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
#[exception]
|
||||
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
|
||||
|
|
|
|||
Loading…
Reference in New Issue