From d3d2d4e4f8e754d8230e0ab60cff683c94e87180 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Wed, 20 Mar 2019 10:29:13 +0000
Subject: [PATCH] enable i/o compensation cell

---
 src/main.rs | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/main.rs b/src/main.rs
index 65f67e8..27c0f05 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -170,6 +170,20 @@ fn main() -> ! {
     rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) });  // pll1p
     while rcc.cfgr.read().sws().bits() != 0b011 {}
 
+    // CSI for I/O compensationc ell
+    rcc.cr.modify(|_, w| w.csion().set_bit());
+    while rcc.cr.read().csirdy().bit_is_clear() {}
+    rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
+
+    let syscfg = dp.SYSCFG;
+    // enable I/O compensation cell
+    syscfg.cccsr.modify(|_, w|
+        w.en().set_bit()
+         .cs().clear_bit()
+         .hslv().clear_bit()
+    );
+    while syscfg.cccsr.read().ready().bit_is_clear() {}
+
     cp.SCB.enable_icache();
     cp.SCB.enable_dcache(&mut cp.CPUID);
     cp.DWT.enable_cycle_counter();