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Merge #65 

65: Tim2 late enable r=jordens a=jordens

does this work for you @cjbe?

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
bors[bot] 2019-11-24 13:33:50 +00:00 committed by GitHub
parent 3cf4f2690c 1140b4fb76
commit d2f8b60c27
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 15 additions and 23 deletions
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19
src/board.rs
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@ -399,8 +399,7 @@ fn tim2_setup(tim2: &pac::TIM2) {
tim2.dier.write(|w| w.ude().set_bit()); tim2.dier.write(|w| w.ude().set_bit());
tim2.egr.write(|w| w.ug().set_bit()); tim2.egr.write(|w| w.ug().set_bit());
tim2.cr1.modify(|_, w| tim2.cr1.modify(|_, w|
w.dir().clear_bit() // up w.dir().clear_bit()); // up
.cen().set_bit()); // enable
} }
fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) {
@ -524,9 +523,19 @@ pub fn init() {
tim2_setup(&dp.TIM2); tim2_setup(&dp.TIM2);
let i2c2 = dp.I2C2; rcc.apb1lenr.modify(|_,w| w.i2c2en().set_bit());
i2c::setup(&rcc, &i2c2); i2c::setup(&dp.I2C2);
eth::setup(&rcc, &dp.SYSCFG); rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
rcc.ahb1enr.modify(|_, w| {
w.eth1macen().set_bit()
.eth1txen().set_bit()
.eth1rxen().set_bit()
});
dp.SYSCFG.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG);
// enable TIM2 this must be late to be able to handle the first ADC SPI
// interrupt in time
dp.TIM2.cr1.modify(|_, w| w.cen().set_bit());
} }

13
src/eth.rs
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@ -85,19 +85,6 @@ use self::cr_consts::*;
// 200 MHz AHB clock = eth_hclk // 200 MHz AHB clock = eth_hclk
const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102; const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
pub fn setup(rcc: &pac::RCC, syscfg: &pac::SYSCFG) {
rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
rcc.ahb1enr.modify(|_, w| {
w.eth1macen().set_bit()
.eth1txen().set_bit()
.eth1rxen().set_bit()
});
syscfg.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
//rcc.ahb1rstr.modify(|_, w| w.eth1macrst().set_bit());
//rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit());
}
pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB,
gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) { gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) {
// PA1 RMII_REF_CLK // PA1 RMII_REF_CLK

6
src/i2c.rs
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@ -21,11 +21,7 @@ pub enum Error {
const N_RETRY: usize = 100; // ~ 10ms @ 100 kHz bus clock const N_RETRY: usize = 100; // ~ 10ms @ 100 kHz bus clock
pub fn setup(rcc: &pac::RCC, i2c: &pac::I2C2) { pub fn setup(i2c: &pac::I2C2) {
rcc.apb1lenr.modify(|_,w|
w.i2c2en().set_bit()
);
// Disable the peripheral before setting timings // Disable the peripheral before setting timings
i2c.cr1.modify(|_, w| w.pe().clear_bit()); i2c.cr1.modify(|_, w| w.pe().clear_bit());