From beecbe3efce987da790c62575a9c7501c1f126d1 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 3 Jun 2020 17:36:43 +0200 Subject: [PATCH 1/7] Refactoring AFE code --- Cargo.lock | 21 +++++++++++++++++++++ Cargo.toml | 1 + src/afe.rs | 43 ++++++++++++++++++++++++++----------------- src/main.rs | 7 +++---- 4 files changed, 51 insertions(+), 21 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 44886bb..f6e7f56 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -178,6 +178,24 @@ dependencies = [ "void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)", ] +[[package]] +name = "enum-iterator" +version = "0.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "enum-iterator-derive 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "enum-iterator-derive" +version = "0.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "proc-macro2 1.0.18 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 1.0.6 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 1.0.30 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "generic-array" version = "0.12.3" @@ -392,6 +410,7 @@ dependencies = [ "cortex-m-rt 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rtfm 0.5.1 (registry+https://github.com/rust-lang/crates.io-index)", "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)", + "enum-iterator 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "heapless 0.5.5 (registry+https://github.com/rust-lang/crates.io-index)", "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)", "mcp23017 0.1.1 (git+https://github.com/mrd0ll4r/mcp23017.git)", @@ -524,6 +543,8 @@ dependencies = [ "checksum cortex-m-rtfm-macros 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c62092f6ff344e9b0adb748f0302ed69889ba2fae1fce446e3788d4726ea73bb" "checksum cortex-m-semihosting 0.3.5 (registry+https://github.com/rust-lang/crates.io-index)" = "113ef0ecffee2b62b58f9380f4469099b30e9f9cbee2804771b4203ba1762cfa" "checksum embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "ee4908a155094da7723c2d60d617b820061e3b4efcc3d9e293d206a5a76c170b" +"checksum enum-iterator 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c79a6321a1197d7730510c7e3f6cb80432dfefecb32426de8cea0aa19b4bb8d7" +"checksum enum-iterator-derive 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1e94aa31f7c0dc764f57896dc615ddd76fc13b0d5dca7eb6cc5e018a5a09ec06" "checksum generic-array 0.12.3 (registry+https://github.com/rust-lang/crates.io-index)" = "c68f0274ae0e023facc3c97b2e00f076be70e254bc851d972503b328db79b2ec" "checksum generic-array 0.13.2 (registry+https://github.com/rust-lang/crates.io-index)" = "0ed1e761351b56f54eb9dcd0cfaca9fd0daecf93918e1cfc01c8a3d26ee7adcd" "checksum hash32 0.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "d4041af86e63ac4298ce40e5cca669066e75b6f1aa3390fe2561ffa5e1d9f4cc" diff --git a/Cargo.toml b/Cargo.toml index acaad2f..f82a952 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -39,6 +39,7 @@ cortex-m-rtfm = "0.5" embedded-hal = "0.2.3" nb = "0.1.2" asm-delay = "0.7.0" +enum-iterator = "0.6.0" [dependencies.mcp23017] git = "https://github.com/mrd0ll4r/mcp23017.git" diff --git a/src/afe.rs b/src/afe.rs index c3d9f3c..dfe0b00 100644 --- a/src/afe.rs +++ b/src/afe.rs @@ -1,6 +1,8 @@ use embedded_hal; +use core::convert::TryFrom; +use enum_iterator::IntoEnumIterator; -#[derive(Copy, Clone, Debug)] +#[derive(Copy, Clone, Debug, IntoEnumIterator)] pub enum Gain { G1 = 0b00, G2 = 0b01, @@ -13,6 +15,20 @@ pub struct ProgrammableGainAmplifier { a1: A1 } +impl TryFrom for Gain { + type Error = (); + + fn try_from(value: u8) -> Result { + for gain in Gain::into_enum_iter() { + if value == gain as u8 { + return Ok(gain) + } + } + + Err(()) + } +} + impl ProgrammableGainAmplifier where A0: embedded_hal::digital::v2::StatefulOutputPin, @@ -43,22 +59,15 @@ where } } - pub fn get_gain(&self) -> Gain { - let lsb_set = self.a0.is_set_high().unwrap(); - let msb_set = self.a1.is_set_high().unwrap(); - - if msb_set { - if lsb_set { - Gain::G10 - } else { - Gain::G5 - } - } else { - if lsb_set { - Gain::G2 - } else { - Gain::G1 - } + pub fn get_gain(&self) -> Result { + let mut code: u8 = 0; + if self.a0.is_set_high().unwrap() { + code |= 0b1; } + if self.a1.is_set_high().unwrap() { + code |= 0b10; + } + + Gain::try_from(code) } } diff --git a/src/main.rs b/src/main.rs index 4401bfe..f6018c8 100644 --- a/src/main.rs +++ b/src/main.rs @@ -252,7 +252,7 @@ const APP: () = { .frame_size(16) .swap_mosi_miso(); - dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 25.mhz(), &clocks) + dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks) }; let dac2_spi = { @@ -269,7 +269,7 @@ const APP: () = { .frame_size(16) .swap_mosi_miso(); - dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 25.mhz(), &clocks) + dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks) }; let pounder_devices = { @@ -487,6 +487,7 @@ const APP: () = { y0 as i16 as u16 ^ 0x8000 }; c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit()); + c.resources.dac1.send(output_ch1).unwrap(); let output_ch2 = { let a: u16 = nb::block!(c.resources.adc2.read()).unwrap(); @@ -495,8 +496,6 @@ const APP: () = { y0 as i16 as u16 ^ 0x8000 }; c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit()); - - c.resources.dac1.send(output_ch1).unwrap(); c.resources.dac2.send(output_ch2).unwrap(); c.resources.dac_pin.set_low().unwrap(); From ade06cbcb874bb9318c08102fcc2e88e63314cec Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 4 Jun 2020 16:56:04 +0200 Subject: [PATCH 2/7] Updating AD9959 api --- src/main.rs | 3 ++- src/pounder/mod.rs | 11 ++++++----- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/main.rs b/src/main.rs index f6018c8..99a8c5f 100644 --- a/src/main.rs +++ b/src/main.rs @@ -303,7 +303,8 @@ const APP: () = { io_update, asm_delay, ad9959::Mode::FourBitSerial, - 100_000_000).unwrap() + 100_000_000, + 5).unwrap() }; let io_expander = { diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index b3ce19f..d29e3bd 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -183,21 +183,22 @@ where 1_u8.wrapping_shl(5)).map_err(|_| Error::I2c)?; devices.mcp23017.all_pin_mode(mcp23017::PinMode::OUTPUT).map_err(|_| Error::I2c)?; - devices.select_onboard_clock()?; + // Select the on-board clock with a 5x prescaler (500MHz). + devices.select_onboard_clock(5u8)?; Ok(devices) } - pub fn select_external_clock(&mut self, frequency: u32) -> Result<(), Error>{ + pub fn select_external_clock(&mut self, frequency: u32, prescaler: u8) -> Result<(), Error>{ self.mcp23017.digital_write(EXT_CLK_SEL_PIN, true).map_err(|_| Error::I2c)?; - self.ad9959.set_clock_frequency(frequency).map_err(|_| Error::DDS)?; + self.ad9959.configure_system_clock(frequency, prescaler).map_err(|_| Error::DDS)?; Ok(()) } - pub fn select_onboard_clock(&mut self) -> Result<(), Error> { + pub fn select_onboard_clock(&mut self, prescaler: u8) -> Result<(), Error> { self.mcp23017.digital_write(EXT_CLK_SEL_PIN, false).map_err(|_| Error::I2c)?; - self.ad9959.set_clock_frequency(100_000_000).map_err(|_| Error::DDS)?; + self.ad9959.configure_system_clock(100_000_000, prescaler).map_err(|_| Error::DDS)?; Ok(()) } From 4dcf2b57bdc540501238b238e0590d064034b88f Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 8 Jun 2020 09:36:28 +0200 Subject: [PATCH 3/7] Updating project structure --- .gitmodules | 3 + Cargo.lock | 390 ++++++------ Cargo.toml | 84 +-- ad9959/.gitignore | 2 + ad9959/Cargo.toml | 11 + ad9959/src/lib.rs | 350 +++++++++++ stabilizer/Cargo.lock | 583 ++++++++++++++++++ stabilizer/Cargo.toml | 76 +++ openocd.gdb => stabilizer/openocd.gdb | 0 {src => stabilizer/src}/afe.rs | 0 {src => stabilizer/src}/eeprom.rs | 0 {src => stabilizer/src}/eth.rs | 0 {src => stabilizer/src}/iir.rs | 0 {src => stabilizer/src}/main.rs | 88 +++ .../src}/pounder/attenuators.rs | 0 {src => stabilizer/src}/pounder/error.rs | 0 {src => stabilizer/src}/pounder/mod.rs | 0 {src => stabilizer/src}/pounder/rf_power.rs | 0 {src => stabilizer/src}/pounder/types.rs | 0 {src => stabilizer/src}/server.rs | 0 stm32h7xx-hal | 1 + 21 files changed, 1309 insertions(+), 279 deletions(-) create mode 100644 .gitmodules create mode 100644 ad9959/.gitignore create mode 100644 ad9959/Cargo.toml create mode 100644 ad9959/src/lib.rs create mode 100644 stabilizer/Cargo.lock create mode 100644 stabilizer/Cargo.toml rename openocd.gdb => stabilizer/openocd.gdb (100%) rename {src => stabilizer/src}/afe.rs (100%) rename {src => stabilizer/src}/eeprom.rs (100%) rename {src => stabilizer/src}/eth.rs (100%) rename {src => stabilizer/src}/iir.rs (100%) rename {src => stabilizer/src}/main.rs (90%) rename {src => stabilizer/src}/pounder/attenuators.rs (100%) rename {src => stabilizer/src}/pounder/error.rs (100%) rename {src => stabilizer/src}/pounder/mod.rs (100%) rename {src => stabilizer/src}/pounder/rf_power.rs (100%) rename {src => stabilizer/src}/pounder/types.rs (100%) rename {src => stabilizer/src}/server.rs (100%) create mode 160000 stm32h7xx-hal diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..5340aad --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "stm32h7xx-hal"] + path = stm32h7xx-hal + url = https://github.com/quartiq/stm32h7xx-hal.git diff --git a/Cargo.lock b/Cargo.lock index f6e7f56..bb74654 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -3,424 +3,462 @@ [[package]] name = "ad9959" version = "0.1.0" -source = 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b/Cargo.toml @@ -1,79 +1,7 @@ -[package] -name = "stabilizer" -version = "0.3.0" -authors = ["Robert Jördens "] -description = "Firmware for the Sinara Stabilizer board (stm32h743, eth, poe, 2 adc, 2 dac)" -categories = ["embedded", "no-std", "hardware-support", "science"] -license = "GPL-3.0-or-later" -keywords = ["ethernet", "stm32h7", "adc", "dac", "physics"] -repository = "https://github.com/quartiq/stabilizer" -readme = "README.md" -documentation = "https://docs.rs/stabilizer/" -edition = "2018" -exclude = [ - ".travis.yml", - ".gitignore", - "doc/", - "doc/*" +[workspace] + +members = [ + "stabilizer", + "stm32h7xx-hal", + "ad9959", ] - -[badges] -travis-ci = { repository = "quartiq/stabilizer", branch = "master" } -maintenance = { status = "experimental" } - -[package.metadata.docs.rs] -features = [] -default-target = "thumbv7em-none-eabihf" - -[dependencies] -cortex-m = { version = "0.6", features = ["const-fn"] } -cortex-m-rt = { version = "0.6", features = ["device"] } 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"rt", "unproven"] - -[features] -semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] -bkpt = [ ] -nightly = ["cortex-m/inline-asm"] - -[profile.dev] -codegen-units = 1 -incremental = false -opt-level = 3 - -[profile.release] -debug = true -lto = true -codegen-units = 1 diff --git a/ad9959/.gitignore b/ad9959/.gitignore new file mode 100644 index 0000000..96ef6c0 --- /dev/null +++ b/ad9959/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/ad9959/Cargo.toml b/ad9959/Cargo.toml new file mode 100644 index 0000000..f234470 --- /dev/null +++ b/ad9959/Cargo.toml @@ -0,0 +1,11 @@ +[package] +name = "ad9959" +version = "0.1.0" +authors = ["Ryan Summers "] +edition = "2018" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +embedded-hal = {version = "0.2.3", features = ["unproven"]} +bit_field = "0.10.0" diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs new file mode 100644 index 0000000..5346bdc --- /dev/null +++ b/ad9959/src/lib.rs @@ -0,0 +1,350 @@ +#![no_std] + +use bit_field::BitField; +use embedded_hal::{ + digital::v2::OutputPin, + blocking::delay::DelayMs, +}; + +/// A device driver for the AD9959 direct digital synthesis (DDS) chip. +/// +/// This chip provides four independently controllable digital-to-analog output sinusoids with +/// configurable phase, amplitude, and frequency. All channels are inherently synchronized as they +/// are derived off a common system clock. +/// +/// The chip contains a configurable PLL and supports system clock frequencies up to 500 MHz. +/// +/// The chip supports a number of serial interfaces to improve data throughput, including normal, +/// dual, and quad SPI configurations. +pub struct Ad9959 { + interface: INTERFACE, + delay: DELAY, + reference_clock_frequency: u32, + system_clock_multiplier: u8, + io_update: UPDATE, +} + +pub trait Interface { + type Error; + + fn configure_mode(&mut self, mode: Mode) -> Result<(), Self::Error>; + + fn write(&mut self, addr: u8, data: &[u8]) -> Result<(), Self::Error>; + + fn read(&mut self, addr: u8, dest: &mut [u8]) -> Result<(), Self::Error>; +} + +#[derive(Copy, Clone, PartialEq)] +pub enum Mode { + SingleBitTwoWire = 0b00, + SingleBitThreeWire = 0b01, + TwoBitSerial = 0b10, + FourBitSerial = 0b11, +} + +/// The configuration registers within the AD9959 DDS device. The values of each register are +/// equivalent to the address. +pub enum Register { + CSR = 0x00, + FR1 = 0x01, + FR2 = 0x02, + CFR = 0x03, + CFTW0 = 0x04, + CPOW0 = 0x05, + ACR = 0x06, + LSRR = 0x07, + RDW = 0x08, + FDW = 0x09, + CW1 = 0x0a, + CW2 = 0x0b, + CW3 = 0x0c, + CW4 = 0x0d, + CW5 = 0x0e, + CW6 = 0x0f, + CW7 = 0x10, + CW8 = 0x11, + CW9 = 0x12, + CW10 = 0x13, + CW11 = 0x14, + CW12 = 0x15, + CW13 = 0x16, + CW14 = 0x17, + CW15 = 0x18, +} + +/// Specifies an output channel of the AD9959 DDS chip. +pub enum Channel { + One = 0, + Two = 1, + Three = 2, + Four = 3, +} + +/// Possible errors generated by the AD9959 driver. +#[derive(Debug)] +pub enum Error { + Interface(InterfaceE), + Bounds, + Pin, + Frequency, +} + +impl From for Error { + fn from(interface_error: InterfaceE) -> Self { + Error::Interface(interface_error) + } +} + +impl Ad9959 +where + INTERFACE: Interface, + DELAY: DelayMs, + UPDATE: OutputPin, + +{ + pub fn new(interface: INTERFACE, + reset_pin: &mut RST, + io_update: UPDATE, + delay: DELAY, + desired_mode: Mode, + clock_frequency: u32, + multiplier: u8) -> Result> + where + RST: OutputPin, + { + let mut ad9959 = Ad9959 { + interface: interface, + io_update: io_update, + delay: delay, + reference_clock_frequency: clock_frequency, + system_clock_multiplier: 1, + }; + + ad9959.io_update.set_low().or_else(|_| Err(Error::Pin))?; + + // Reset the AD9959 + reset_pin.set_high().or_else(|_| Err(Error::Pin))?; + + // Delay for a clock cycle to allow the device to reset. + ad9959.delay.delay_ms((1000.0 / clock_frequency as f32) as u8); + + reset_pin.set_low().or_else(|_| Err(Error::Pin))?; + + ad9959.interface.configure_mode(Mode::SingleBitTwoWire)?; + + // Program the interface configuration in the AD9959. Default to all channels enabled. + let mut csr: [u8; 1] = [0xF0]; + csr[0].set_bits(1..3, desired_mode as u8); + ad9959.interface.write(0, &csr)?; + + // Configure the interface to the desired mode. + ad9959.interface.configure_mode(Mode::FourBitSerial)?; + + // Latch the configuration registers to make them active. + ad9959.latch_configuration()?; + + ad9959.interface.configure_mode(desired_mode)?; + + // Set the clock frequency to configure the device as necessary. + ad9959.configure_system_clock(clock_frequency, multiplier)?; + Ok(ad9959) + } + + fn latch_configuration(&mut self) -> Result<(), Error> { + self.io_update.set_high().or_else(|_| Err(Error::Pin))?; + // The SYNC_CLK is 1/4 the system clock frequency. The IO_UPDATE pin must be latched for one + // full SYNC_CLK pulse to register. For safety, we latch for 5 here. + self.delay.delay_ms((5000.0 / self.system_clock_frequency()) as u8); + self.io_update.set_low().or_else(|_| Err(Error::Pin))?; + + Ok(()) + } + + /// Configure the internal system clock of the chip. + /// + /// Arguments: + /// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core. + /// * `prescaler` - The frequency prescaler of the system clock. Must be 1 or 4-20. + /// + /// Returns: + /// The actual frequency configured for the internal system clock. + pub fn configure_system_clock(&mut self, + reference_clock_frequency: u32, + prescaler: u8) -> Result> + { + self.reference_clock_frequency = reference_clock_frequency; + + if prescaler != 1 && (prescaler > 20 || prescaler < 4) { + return Err(Error::Bounds); + } + + let frequency = prescaler as f64 * self.reference_clock_frequency as f64; + if frequency > 500_000_000.0f64 { + return Err(Error::Frequency); + } + + // TODO: Update / disable any enabled channels? + let mut fr1: [u8; 3] = [0, 0, 0]; + self.interface.read(Register::FR1 as u8, &mut fr1)?; + fr1[0].set_bits(2..=6, prescaler); + + let vco_range = frequency > 255e6; + fr1[0].set_bit(7, vco_range); + + self.interface.write(Register::FR1 as u8, &fr1)?; + self.system_clock_multiplier = prescaler; + + Ok(self.system_clock_frequency()) + } + + /// Perform a self-test of the communication interface. + /// + /// Note: + /// This modifies the existing channel enables. They are restored upon exit. + /// + /// Returns: + /// True if the self test succeeded. False otherwise. + pub fn self_test(&mut self) -> Result> { + let mut csr: [u8; 1] = [0]; + self.interface.read(Register::CSR as u8, &mut csr)?; + let old_csr = csr[0]; + + // Enable all channels. + csr[0].set_bits(4..8, 0xF); + self.interface.write(Register::CSR as u8, &csr)?; + + // Read back the enable. + csr[0] = 0; + self.interface.read(Register::CSR as u8, &mut csr)?; + if csr[0].get_bits(4..8) != 0xF { + return Ok(false); + } + + // Clear all channel enables. + csr[0].set_bits(4..8, 0x0); + self.interface.write(Register::CSR as u8, &csr)?; + + // Read back the enable. + csr[0] = 0xFF; + self.interface.read(Register::CSR as u8, &mut csr)?; + if csr[0].get_bits(4..8) != 0 { + return Ok(false); + } + + // Restore the CSR. + csr[0] = old_csr; + self.interface.write(Register::CSR as u8, &csr)?; + + Ok(true) + } + + fn system_clock_frequency(&self) -> f64 { + self.system_clock_multiplier as f64 * self.reference_clock_frequency as f64 + } + + /// Enable an output channel. + pub fn enable_channel(&mut self, channel: Channel) -> Result<(), Error> { + let mut csr: [u8; 1] = [0]; + self.interface.read(Register::CSR as u8, &mut csr)?; + csr[0].set_bit(channel as usize + 4, true); + self.interface.write(Register::CSR as u8, &csr)?; + + Ok(()) + } + + /// Disable an output channel. + pub fn disable_channel(&mut self, channel: Channel) -> Result<(), Error> { + let mut csr: [u8; 1] = [0]; + self.interface.read(Register::CSR as u8, &mut csr)?; + csr[0].set_bit(channel as usize + 4, false); + self.interface.write(Register::CSR as u8, &csr)?; + + Ok(()) + } + + fn modify_channel(&mut self, channel: Channel, register: Register, data: &[u8]) -> Result<(), Error> { + let mut csr: [u8; 1] = [0]; + self.interface.read(Register::CSR as u8, &mut csr)?; + + let mut new_csr = csr; + new_csr[0].set_bits(4..8, 0); + new_csr[0].set_bit(4 + channel as usize, true); + + self.interface.write(Register::CSR as u8, &new_csr)?; + + self.interface.write(register as u8, &data)?; + + // Latch the configuration and restore the previous CSR. Note that the re-enable of the + // channel happens immediately, so the CSR update does not need to be latched. + self.latch_configuration()?; + self.interface.write(Register::CSR as u8, &csr)?; + + Ok(()) + } + + /// Configure the phase of a specified channel. + /// + /// Arguments: + /// * `channel` - The channel to configure the frequency of. + /// * `phase_turns` - The desired phase offset in normalized turns. + /// + /// Returns: + /// The actual programmed phase offset of the channel in degrees. + pub fn set_phase(&mut self, channel: Channel, phase_turns: f32) -> Result> { + if phase_turns > 1.0 || phase_turns < 0.0 { + return Err(Error::Bounds); + } + + let phase_offset: u16 = (phase_turns * 1u32.wrapping_shl(14) as f32) as u16; + self.modify_channel(channel, Register::CPOW0, &phase_offset.to_be_bytes())?; + Ok((phase_offset as f32 / 1u32.wrapping_shl(14) as f32) * 360.0) + } + + /// Configure the amplitude of a specified channel. + /// + /// Arguments: + /// * `channel` - The channel to configure the frequency of. + /// * `amplitude` - A normalized amplitude setting [0, 1]. + /// + /// Returns: + /// The actual normalized amplitude of the channel relative to full-scale range. + pub fn set_amplitude(&mut self, channel: Channel, amplitude: f32) -> Result> { + if amplitude < 0.0 || amplitude > 1.0 { + return Err(Error::Bounds); + } + + let amplitude_control: u16 = (amplitude / 1u16.wrapping_shl(10) as f32) as u16; + let mut acr: [u8; 3] = [0, amplitude_control.to_be_bytes()[0], amplitude_control.to_be_bytes()[1]]; + + // Enable the amplitude multiplier for the channel if required. The amplitude control has + // full-scale at 0x3FF (amplitude of 1), so the multiplier should be disabled whenever + // full-scale is used. + acr[1].set_bit(4, amplitude_control >= 1u16.wrapping_shl(10)); + + self.modify_channel(channel, Register::ACR, &acr)?; + + Ok(amplitude_control as f32 / 1_u16.wrapping_shl(10) as f32) + } + + /// Configure the frequency of a specified channel. + /// + /// Arguments: + /// * `channel` - The channel to configure the frequency of. + /// * `frequency` - The desired output frequency in Hz. + /// + /// Returns: + /// The actual programmed frequency of the channel. + pub fn set_frequency(&mut self, channel: Channel, frequency: f64) -> Result> { + if frequency < 0.0 || frequency > self.system_clock_frequency() { + return Err(Error::Bounds); + } + + // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the + // frequency tuning word and f_s is the system clock rate. + let tuning_word: u32 = ((frequency as f64 / self.system_clock_frequency()) + * 1u64.wrapping_shl(32) as f64) as u32; + + self.modify_channel(channel, Register::CFTW0, &tuning_word.to_be_bytes())?; + Ok((tuning_word as f64 / 1u64.wrapping_shl(32) as f64) * self.system_clock_frequency()) + } +} diff --git a/stabilizer/Cargo.lock b/stabilizer/Cargo.lock new file mode 100644 index 0000000..f6e7f56 --- /dev/null +++ b/stabilizer/Cargo.lock @@ -0,0 +1,583 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +[[package]] +name = "ad9959" +version = "0.1.0" +source = "git+https://github.com/quartiq/ad9959.git?branch=feature/basic-driver#b45bce3f0dd7a58b5a272b778001dc9422c2c160" +dependencies = [ + "bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)", + "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "aligned" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" + +[[package]] +name = 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+ +[badges] +travis-ci = { repository = "quartiq/stabilizer", branch = "master" } +maintenance = { status = "experimental" } + +[package.metadata.docs.rs] +features = [] +default-target = "thumbv7em-none-eabihf" + +[dependencies] +cortex-m = { version = "0.6", features = ["const-fn"] } +cortex-m-rt = { version = "0.6", features = ["device"] } +cortex-m-log = { version = "0.6", features = ["log-integration"] } +log = "0.4" +panic-semihosting = { version = "0.5", optional = true } +panic-halt = "0.2" +serde = { version = "1.0", features = ["derive"], default-features = false } +heapless = "0.5" +serde-json-core = "0.1" +cortex-m-rtfm = "0.5" +embedded-hal = "0.2.3" +nb = "0.1.2" +asm-delay = "0.7.0" +enum-iterator = "0.6.0" + +[dependencies.mcp23017] +git = "https://github.com/mrd0ll4r/mcp23017.git" + +[dependencies.smoltcp] +version = "0.6" +features = ["ethernet", "proto-ipv4", "socket-tcp", "proto-ipv6"] +default-features = false + +[dependencies.ad9959] +path = "../ad9959" + +[dependencies.stm32h7-ethernet] +git = "https://github.com/quartiq/stm32h7-ethernet.git" +features = ["stm32h743v"] + +[dependencies.stm32h7xx-hal] +path = "../stm32h7xx-hal/" +features = ["stm32h743v", "rt", "unproven"] + +[features] +semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] +bkpt = [ ] +nightly = ["cortex-m/inline-asm"] + +[profile.dev] +codegen-units = 1 +incremental = false +opt-level = 3 + +[profile.release] +debug = true +lto = true +codegen-units = 1 diff --git a/openocd.gdb b/stabilizer/openocd.gdb similarity index 100% rename from openocd.gdb rename to stabilizer/openocd.gdb diff --git a/src/afe.rs b/stabilizer/src/afe.rs similarity index 100% rename from src/afe.rs rename to stabilizer/src/afe.rs diff --git a/src/eeprom.rs b/stabilizer/src/eeprom.rs similarity index 100% rename from src/eeprom.rs rename to stabilizer/src/eeprom.rs diff --git a/src/eth.rs b/stabilizer/src/eth.rs similarity index 100% rename from src/eth.rs rename to stabilizer/src/eth.rs diff --git a/src/iir.rs b/stabilizer/src/iir.rs similarity index 100% rename from src/iir.rs rename to stabilizer/src/iir.rs diff --git a/src/main.rs b/stabilizer/src/main.rs similarity index 90% rename from src/main.rs rename to stabilizer/src/main.rs index 99a8c5f..07f11b6 100644 --- a/src/main.rs +++ b/stabilizer/src/main.rs @@ -98,6 +98,8 @@ static mut NET_STORE: NetStorage = NetStorage { const SCALE: f32 = ((1 << 15) - 1) as f32; +const SPI_START_CODE: u32 = 0x201; + // static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); const TCP_RX_BUFFER_SIZE: usize = 8192; @@ -111,6 +113,86 @@ type AFE2 = afe::ProgrammableGainAmplifier< hal::gpio::gpiod::PD14>, hal::gpio::gpiod::PD15>>; + + + + +fn dma1_setup( + dma1: &pac::DMA1, + dmamux1: &pac::DMAMUX1, + ma: usize, + pa0: usize, + pa1: usize, +) { + dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); + while dma1.st[0].cr.read().en().bit_is_set() {} + + dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) }); + dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) }); + dma1.st[0].ndtr.write(|w| w.ndt().bits(1)); + dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up()); + dma1.st[0].cr.modify(|_, w| { + w.pl() + .medium() + .circ() + .enabled() + .msize() + .bits32() + .minc() + .fixed() + .mburst() + .single() + .psize() + .bits32() + .pinc() + .fixed() + .pburst() + .single() + .dbm() + .disabled() + .dir() + .memory_to_peripheral() + .pfctrl() + .dma() + }); + dma1.st[0].fcr.modify(|_, w| w.dmdis().clear_bit()); + dma1.st[0].cr.modify(|_, w| w.en().set_bit()); + + dma1.st[1].cr.modify(|_, w| w.en().clear_bit()); + while dma1.st[1].cr.read().en().bit_is_set() {} + + dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) }); + dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) }); + dma1.st[1].ndtr.write(|w| w.ndt().bits(1)); + dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up()); + dma1.st[1].cr.modify(|_, w| { + w.pl() + .medium() + .circ() + .enabled() + .msize() + .bits32() + .minc() + .fixed() + .mburst() + .single() + .psize() + .bits32() + .pinc() + .fixed() + .pburst() + .single() + .dbm() + .disabled() + .dir() + .memory_to_peripheral() + .pfctrl() + .dma() + }); + dma1.st[1].fcr.modify(|_, w| w.dmdis().clear_bit()); + dma1.st[1].cr.modify(|_, w| w.en().set_bit()); +} + #[rtfm::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtfm::cyccnt::CYCCNT)] const APP: () = { struct Resources { @@ -442,6 +524,12 @@ const APP: () = { let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks); timer2.listen(hal::timer::Event::TimeOut); + dma1_setup(&dp.DMA1, + &dp.DMAMUX1, + &SPI_START_CODE as *const _ as usize, + &adc1_spi.spi.cr1 as *const _ as usize, + &adc2_spi.spi.cr1 as *const _ as usize); + init::LateResources { adc1: adc1_spi, dac1: dac1_spi, diff --git a/src/pounder/attenuators.rs b/stabilizer/src/pounder/attenuators.rs similarity index 100% rename from src/pounder/attenuators.rs rename to stabilizer/src/pounder/attenuators.rs diff --git a/src/pounder/error.rs b/stabilizer/src/pounder/error.rs similarity index 100% rename from src/pounder/error.rs rename to stabilizer/src/pounder/error.rs diff --git a/src/pounder/mod.rs b/stabilizer/src/pounder/mod.rs similarity index 100% rename from src/pounder/mod.rs rename to stabilizer/src/pounder/mod.rs diff --git a/src/pounder/rf_power.rs b/stabilizer/src/pounder/rf_power.rs similarity index 100% rename from src/pounder/rf_power.rs rename to stabilizer/src/pounder/rf_power.rs diff --git a/src/pounder/types.rs b/stabilizer/src/pounder/types.rs similarity index 100% rename from src/pounder/types.rs rename to stabilizer/src/pounder/types.rs diff --git a/src/server.rs b/stabilizer/src/server.rs similarity index 100% rename from src/server.rs rename to stabilizer/src/server.rs diff --git a/stm32h7xx-hal b/stm32h7xx-hal new file mode 160000 index 0000000..ba7d21a --- /dev/null +++ b/stm32h7xx-hal @@ -0,0 +1 @@ +Subproject commit ba7d21a018752c2cf9303470badfa8dbf14dc3aa From 0815a4cff5aec39df0d529e936f8bf4c2394500f Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 8 Jun 2020 18:11:14 +0200 Subject: [PATCH 4/7] Updating structure, adding DMA triggered transfers --- Cargo.toml | 10 + stabilizer/openocd.gdb => openocd.gdb | 3 +- stabilizer/Cargo.toml | 9 - stabilizer/src/main.rs | 319 ++++++++++---------------- stm32h7xx-hal | 2 +- 5 files changed, 130 insertions(+), 213 deletions(-) rename stabilizer/openocd.gdb => openocd.gdb (95%) diff --git a/Cargo.toml b/Cargo.toml index de36a31..05df738 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -5,3 +5,13 @@ members = [ "stm32h7xx-hal", "ad9959", ] + +[profile.dev] +codegen-units = 1 +incremental = false +opt-level = 3 + +[profile.release] +debug = true +lto = true +codegen-units = 1 diff --git a/stabilizer/openocd.gdb b/openocd.gdb similarity index 95% rename from stabilizer/openocd.gdb rename to openocd.gdb index 1728d7e..e903a33 100644 --- a/stabilizer/openocd.gdb +++ b/openocd.gdb @@ -16,7 +16,7 @@ break rust_begin_unwind load # tbreak cortex_m_rt::reset_handler -# monitor reset halt +monitor reset halt # cycle counter delta tool, place two bkpts around the section set var $cc=0xe0001004 @@ -26,4 +26,3 @@ set var $t0=*$cc continue end #set var $t0=*$cc -continue diff --git a/stabilizer/Cargo.toml b/stabilizer/Cargo.toml index d614c54..ffbd1e4 100644 --- a/stabilizer/Cargo.toml +++ b/stabilizer/Cargo.toml @@ -65,12 +65,3 @@ semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] bkpt = [ ] nightly = ["cortex-m/inline-asm"] -[profile.dev] -codegen-units = 1 -incremental = false -opt-level = 3 - -[profile.release] -debug = true -lto = true -codegen-units = 1 diff --git a/stabilizer/src/main.rs b/stabilizer/src/main.rs index 07f11b6..1840360 100644 --- a/stabilizer/src/main.rs +++ b/stabilizer/src/main.rs @@ -1,4 +1,4 @@ -#![deny(warnings)] +//#![deny(warnings)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -114,85 +114,6 @@ type AFE2 = afe::ProgrammableGainAmplifier< hal::gpio::gpiod::PD15>>; - - - -fn dma1_setup( - dma1: &pac::DMA1, - dmamux1: &pac::DMAMUX1, - ma: usize, - pa0: usize, - pa1: usize, -) { - dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); - while dma1.st[0].cr.read().en().bit_is_set() {} - - dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) }); - dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) }); - dma1.st[0].ndtr.write(|w| w.ndt().bits(1)); - dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up()); - dma1.st[0].cr.modify(|_, w| { - w.pl() - .medium() - .circ() - .enabled() - .msize() - .bits32() - .minc() - .fixed() - .mburst() - .single() - .psize() - .bits32() - .pinc() - .fixed() - .pburst() - .single() - .dbm() - .disabled() - .dir() - .memory_to_peripheral() - .pfctrl() - .dma() - }); - dma1.st[0].fcr.modify(|_, w| w.dmdis().clear_bit()); - dma1.st[0].cr.modify(|_, w| w.en().set_bit()); - - dma1.st[1].cr.modify(|_, w| w.en().clear_bit()); - while dma1.st[1].cr.read().en().bit_is_set() {} - - dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) }); - dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) }); - dma1.st[1].ndtr.write(|w| w.ndt().bits(1)); - dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up()); - dma1.st[1].cr.modify(|_, w| { - w.pl() - .medium() - .circ() - .enabled() - .msize() - .bits32() - .minc() - .fixed() - .mburst() - .single() - .psize() - .bits32() - .pinc() - .fixed() - .pburst() - .single() - .dbm() - .disabled() - .dir() - .memory_to_peripheral() - .pfctrl() - .dma() - }); - dma1.st[1].fcr.modify(|_, w| w.dmdis().clear_bit()); - dma1.st[1].cr.modify(|_, w| w.en().set_bit()); -} - #[rtfm::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtfm::cyccnt::CYCCNT)] const APP: () = { struct Resources { @@ -206,15 +127,13 @@ const APP: () = { eeprom_i2c: hal::i2c::I2c, - dbg_pin: hal::gpio::gpioc::PC6>, - dac_pin: hal::gpio::gpiob::PB15>, timer: hal::timer::Timer, net_interface: net::iface::EthernetInterface<'static, 'static, 'static, ethernet::EthernetDMA<'static>>, _eth_mac: ethernet::EthernetMAC, mac_addr: net::wire::EthernetAddress, - pounder: pounder::PounderDevices, + //pounder: pounder::PounderDevices, #[init([[0.; 5]; 2])] iir_state: [IIRState; 2], @@ -282,8 +201,9 @@ const APP: () = { }) .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() - .cs_delay(220e-9) - .frame_size(16); + .transfer_size(1) + .frame_size(16) + .cs_delay(220e-9); let mut spi = dp.SPI2.spi( (spi_sck, spi_miso, hal::spi::NoMosi), @@ -291,7 +211,7 @@ const APP: () = { 50.mhz(), &clocks); - spi.listen(hal::spi::Event::Rxp); + spi.listen(hal::spi::Event::Eot); spi }; @@ -308,21 +228,24 @@ const APP: () = { }) .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() + .transfer_size(1) .frame_size(16) .cs_delay(220e-9); - let spi = dp.SPI3.spi( + let mut spi = dp.SPI3.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks); + spi.listen(hal::spi::Event::Eot); + spi }; let dac1_spi = { - let spi_miso = gpioe.pe5.into_alternate_af5(); - let spi_sck = gpioe.pe2.into_alternate_af5(); + let spi_miso = gpioe.pe5.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpioe.pe2.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh); let _spi_nss = gpioe.pe4.into_alternate_af5(); let config = hal::spi::Config::new(hal::spi::Mode{ @@ -331,15 +254,17 @@ const APP: () = { }) .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() + .transfer_size(1) .frame_size(16) .swap_mosi_miso(); - dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks) + let spi = dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks); + spi }; let dac2_spi = { - let spi_miso = gpiof.pf8.into_alternate_af5(); - let spi_sck = gpiof.pf7.into_alternate_af5(); + let spi_miso = gpiof.pf8.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpiof.pf7.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh); let _spi_nss = gpiof.pf6.into_alternate_af5(); let config = hal::spi::Config::new(hal::spi::Mode{ @@ -348,93 +273,96 @@ const APP: () = { }) .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() + .transfer_size(1) .frame_size(16) .swap_mosi_miso(); - dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks) + let spi = dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks); + + spi }; - let pounder_devices = { - let ad9959 = { - let qspi_interface = { - // Instantiate the QUADSPI pins and peripheral interface. - // TODO: Place these into a pins structure that is provided to the QSPI - // constructor. - let _qspi_clk = gpiob.pb2.into_alternate_af9(); - let _qspi_ncs = gpioc.pc11.into_alternate_af9(); - let _qspi_io0 = gpioe.pe7.into_alternate_af10(); - let _qspi_io1 = gpioe.pe8.into_alternate_af10(); - let _qspi_io2 = gpioe.pe9.into_alternate_af10(); - let _qspi_io3 = gpioe.pe10.into_alternate_af10(); + // let pounder_devices = { + // let ad9959 = { + // let qspi_interface = { + // // Instantiate the QUADSPI pins and peripheral interface. + // // TODO: Place these into a pins structure that is provided to the QSPI + // // constructor. + // let _qspi_clk = gpiob.pb2.into_alternate_af9(); + // let _qspi_ncs = gpioc.pc11.into_alternate_af9(); + // let _qspi_io0 = gpioe.pe7.into_alternate_af10(); + // let _qspi_io1 = gpioe.pe8.into_alternate_af10(); + // let _qspi_io2 = gpioe.pe9.into_alternate_af10(); + // let _qspi_io3 = gpioe.pe10.into_alternate_af10(); - let qspi = hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()).unwrap(); - pounder::QspiInterface::new(qspi).unwrap() - }; + // let qspi = hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()).unwrap(); + // pounder::QspiInterface::new(qspi).unwrap() + // }; - let mut reset_pin = gpioa.pa0.into_push_pull_output(); - let io_update = gpiog.pg7.into_push_pull_output(); + // let mut reset_pin = gpioa.pa0.into_push_pull_output(); + // let io_update = gpiog.pg7.into_push_pull_output(); - let asm_delay = { - let frequency_hz = clocks.clocks.c_ck().0; - asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz (frequency_hz)) - }; + // let asm_delay = { + // let frequency_hz = clocks.clocks.c_ck().0; + // asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz (frequency_hz)) + // }; - ad9959::Ad9959::new(qspi_interface, - &mut reset_pin, - io_update, - asm_delay, - ad9959::Mode::FourBitSerial, - 100_000_000, - 5).unwrap() - }; + // ad9959::Ad9959::new(qspi_interface, + // &mut reset_pin, + // io_update, + // asm_delay, + // ad9959::Mode::FourBitSerial, + // 100_000_000, + // 5).unwrap() + // }; - let io_expander = { - let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); - let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); - let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks); - mcp23017::MCP23017::default(i2c1).unwrap() - }; + // let io_expander = { + // let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); + // let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); + // let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks); + // mcp23017::MCP23017::default(i2c1).unwrap() + // }; - let spi = { - let spi_mosi = gpiod.pd7.into_alternate_af5(); - let spi_miso = gpioa.pa6.into_alternate_af5(); - let spi_sck = gpiog.pg11.into_alternate_af5(); + // let spi = { + // let spi_mosi = gpiod.pd7.into_alternate_af5(); + // let spi_miso = gpioa.pa6.into_alternate_af5(); + // let spi_sck = gpiog.pg11.into_alternate_af5(); - let config = hal::spi::Config::new(hal::spi::Mode{ - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .frame_size(8); + // let config = hal::spi::Config::new(hal::spi::Mode{ + // polarity: hal::spi::Polarity::IdleHigh, + // phase: hal::spi::Phase::CaptureOnSecondTransition, + // }) + // .frame_size(8); - dp.SPI1.spi((spi_sck, spi_miso, spi_mosi), config, 25.mhz(), &clocks) - }; + // dp.SPI1.spi((spi_sck, spi_miso, spi_mosi), config, 25.mhz(), &clocks) + // }; - let adc1 = { - let mut adc = dp.ADC1.adc(&mut delay, &mut clocks); - adc.calibrate(); + // let adc1 = { + // let mut adc = dp.ADC1.adc(&mut delay, &mut clocks); + // adc.calibrate(); - adc.enable() - }; + // adc.enable() + // }; - let adc2 = { - let mut adc = dp.ADC2.adc(&mut delay, &mut clocks); - adc.calibrate(); + // let adc2 = { + // let mut adc = dp.ADC2.adc(&mut delay, &mut clocks); + // adc.calibrate(); - adc.enable() - }; + // adc.enable() + // }; - let adc1_in_p = gpiof.pf11.into_analog(); - let adc2_in_p = gpiof.pf14.into_analog(); + // let adc1_in_p = gpiof.pf11.into_analog(); + // let adc2_in_p = gpiof.pf14.into_analog(); - pounder::PounderDevices::new(io_expander, - ad9959, - spi, - adc1, - adc2, - adc1_in_p, - adc2_in_p).unwrap() - }; + // pounder::PounderDevices::new(io_expander, + // ad9959, + // spi, + // adc1, + // adc2, + // adc1_in_p, + // adc2_in_p).unwrap() + // }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); let mut fp_led_1 = gpiod.pd6.into_push_pull_output(); @@ -514,21 +442,24 @@ const APP: () = { // Utilize the cycle counter for RTFM scheduling. cp.DWT.enable_cycle_counter(); - let mut debug_pin = gpioc.pc6.into_push_pull_output(); - debug_pin.set_low().unwrap(); + let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks); + dma.configure_m2p_stream(hal::dma::Stream::One, + &SPI_START_CODE as *const _ as u32, + &adc1_spi.spi.cr1 as *const _ as u32, + hal::dma::DMAREQ_ID::TIM2_CH1); - let mut dac_pin = gpiob.pb15.into_push_pull_output(); - dac_pin.set_low().unwrap(); + dma.configure_m2p_stream(hal::dma::Stream::Two, + &SPI_START_CODE as *const _ as u32, + &adc2_spi.spi.cr1 as *const _ as u32, + hal::dma::DMAREQ_ID::TIM2_CH2); // Configure timer 2 to trigger conversions for the ADC let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks); - timer2.listen(hal::timer::Event::TimeOut); + timer2.configure_channel(hal::timer::Channel::One, 0.25); + timer2.configure_channel(hal::timer::Channel::Two, 0.75); - dma1_setup(&dp.DMA1, - &dp.DMAMUX1, - &SPI_START_CODE as *const _ as usize, - &adc1_spi.spi.cr1 as *const _ as usize, - &adc2_spi.spi.cr1 as *const _ as usize); + timer2.listen(hal::timer::Event::ChannelOneDma); + timer2.listen(hal::timer::Event::ChannelTwoDma); init::LateResources { adc1: adc1_spi, @@ -538,10 +469,8 @@ const APP: () = { _afe1: afe1, _afe2: afe2, - dbg_pin: debug_pin, - dac_pin: dac_pin, timer: timer2, - pounder: pounder_devices, + //pounder: pounder_devices, eeprom_i2c: eeprom_i2c, net_interface: network_interface, @@ -550,46 +479,34 @@ const APP: () = { } } - #[task(binds = TIM2, resources = [dbg_pin, timer, adc1, adc2])] - fn tim2(mut c: tim2::Context) { - c.resources.timer.clear_uif_bit(); - c.resources.dbg_pin.set_high().unwrap(); + #[task(binds = SPI3, resources = [adc2, dac2, iir_state, iir_ch], priority = 2)] + fn spi3(c: spi3::Context) { + c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit()); - // Start a SPI transaction on ADC0 and ADC1 - c.resources.adc1.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit())); - c.resources.adc2.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit())); + let output: u16 = { + let a: u16 = c.resources.adc2.read().unwrap(); + let x0 = f32::from(a as i16); + let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); + y0 as i16 as u16 ^ 0x8000 + }; - c.resources.dbg_pin.set_low().unwrap(); + c.resources.dac2.spi.ifcr.write(|w| w.eotc().set_bit().txtfc().set_bit()); + c.resources.dac2.send(output).unwrap(); } - #[task(binds = SPI2, resources = [adc1, dac1, adc2, dac2, iir_state, iir_ch, dac_pin], priority = 2)] - fn adc_spi(c: adc_spi::Context) { - #[cfg(feature = "bkpt")] - cortex_m::asm::bkpt(); + #[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)] + fn spi2(c: spi2::Context) { + c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit()); - c.resources.dac_pin.set_high().unwrap(); - - let output_ch1 = { + let output: u16 = { let a: u16 = c.resources.adc1.read().unwrap(); let x0 = f32::from(a as i16); let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); y0 as i16 as u16 ^ 0x8000 }; - c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit()); - c.resources.dac1.send(output_ch1).unwrap(); - let output_ch2 = { - let a: u16 = nb::block!(c.resources.adc2.read()).unwrap(); - let x0 = f32::from(a as i16); - let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); - y0 as i16 as u16 ^ 0x8000 - }; - c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit()); - c.resources.dac2.send(output_ch2).unwrap(); - - c.resources.dac_pin.set_low().unwrap(); - #[cfg(feature = "bkpt")] - cortex_m::asm::bkpt(); + c.resources.dac1.spi.ifcr.write(|w| w.eotc().set_bit().txtfc().set_bit()); + c.resources.dac1.send(output).unwrap(); } #[idle(resources=[net_interface, mac_addr, iir_state, iir_ch])] diff --git a/stm32h7xx-hal b/stm32h7xx-hal index ba7d21a..2236b57 160000 --- a/stm32h7xx-hal +++ b/stm32h7xx-hal @@ -1 +1 @@ -Subproject commit ba7d21a018752c2cf9303470badfa8dbf14dc3aa +Subproject commit 2236b578b48aa195679dd65515f595f491f88513 From 86c4c1ea5e4315a0f35d8b0d53799069f6bd210f Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 8 Jun 2020 18:17:51 +0200 Subject: [PATCH 5/7] Removing pounder-specific code --- Cargo.lock | 15 -- Cargo.toml | 1 - ad9959/.gitignore | 2 - ad9959/Cargo.toml | 11 - ad9959/src/lib.rs | 350 -------------------------- stabilizer/Cargo.toml | 3 - stabilizer/src/main.rs | 93 +------ stabilizer/src/pounder/attenuators.rs | 57 ----- stabilizer/src/pounder/error.rs | 11 - stabilizer/src/pounder/mod.rs | 265 ------------------- stabilizer/src/pounder/rf_power.rs | 14 -- stabilizer/src/pounder/types.rs | 16 -- 12 files changed, 1 insertion(+), 837 deletions(-) delete mode 100644 ad9959/.gitignore delete mode 100644 ad9959/Cargo.toml delete mode 100644 ad9959/src/lib.rs delete mode 100644 stabilizer/src/pounder/attenuators.rs delete mode 100644 stabilizer/src/pounder/error.rs delete mode 100644 stabilizer/src/pounder/mod.rs delete mode 100644 stabilizer/src/pounder/rf_power.rs delete mode 100644 stabilizer/src/pounder/types.rs diff --git a/Cargo.lock b/Cargo.lock index bb74654..3957ff6 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1,13 +1,5 @@ # This file is automatically @generated by Cargo. # It is not intended for manual editing. -[[package]] -name = "ad9959" -version = "0.1.0" -dependencies = [ - "bit_field", - "embedded-hal", -] - [[package]] name = "aligned" version = "0.3.2" @@ -54,12 +46,6 @@ dependencies = [ "rustc_version", ] -[[package]] -name = "bit_field" -version = "0.10.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0" - [[package]] name = "bitflags" version = "1.2.1" @@ -441,7 +427,6 @@ dependencies = [ name = "stabilizer" version = "0.3.0" dependencies = [ - "ad9959", "asm-delay", "cortex-m", "cortex-m-log", diff --git a/Cargo.toml b/Cargo.toml index 05df738..ac00002 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -3,7 +3,6 @@ members = [ "stabilizer", "stm32h7xx-hal", - "ad9959", ] [profile.dev] diff --git a/ad9959/.gitignore b/ad9959/.gitignore deleted file mode 100644 index 96ef6c0..0000000 --- a/ad9959/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/target -Cargo.lock diff --git a/ad9959/Cargo.toml b/ad9959/Cargo.toml deleted file mode 100644 index f234470..0000000 --- a/ad9959/Cargo.toml +++ /dev/null @@ -1,11 +0,0 @@ -[package] -name = "ad9959" -version = "0.1.0" -authors = ["Ryan Summers "] -edition = "2018" - -# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html - -[dependencies] -embedded-hal = {version = "0.2.3", features = ["unproven"]} -bit_field = "0.10.0" diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs deleted file mode 100644 index 5346bdc..0000000 --- a/ad9959/src/lib.rs +++ /dev/null @@ -1,350 +0,0 @@ -#![no_std] - -use bit_field::BitField; -use embedded_hal::{ - digital::v2::OutputPin, - blocking::delay::DelayMs, -}; - -/// A device driver for the AD9959 direct digital synthesis (DDS) chip. -/// -/// This chip provides four independently controllable digital-to-analog output sinusoids with -/// configurable phase, amplitude, and frequency. All channels are inherently synchronized as they -/// are derived off a common system clock. -/// -/// The chip contains a configurable PLL and supports system clock frequencies up to 500 MHz. -/// -/// The chip supports a number of serial interfaces to improve data throughput, including normal, -/// dual, and quad SPI configurations. -pub struct Ad9959 { - interface: INTERFACE, - delay: DELAY, - reference_clock_frequency: u32, - system_clock_multiplier: u8, - io_update: UPDATE, -} - -pub trait Interface { - type Error; - - fn configure_mode(&mut self, mode: Mode) -> Result<(), Self::Error>; - - fn write(&mut self, addr: u8, data: &[u8]) -> Result<(), Self::Error>; - - fn read(&mut self, addr: u8, dest: &mut [u8]) -> Result<(), Self::Error>; -} - -#[derive(Copy, Clone, PartialEq)] -pub enum Mode { - SingleBitTwoWire = 0b00, - SingleBitThreeWire = 0b01, - TwoBitSerial = 0b10, - FourBitSerial = 0b11, -} - -/// The configuration registers within the AD9959 DDS device. The values of each register are -/// equivalent to the address. -pub enum Register { - CSR = 0x00, - FR1 = 0x01, - FR2 = 0x02, - CFR = 0x03, - CFTW0 = 0x04, - CPOW0 = 0x05, - ACR = 0x06, - LSRR = 0x07, - RDW = 0x08, - FDW = 0x09, - CW1 = 0x0a, - CW2 = 0x0b, - CW3 = 0x0c, - CW4 = 0x0d, - CW5 = 0x0e, - CW6 = 0x0f, - CW7 = 0x10, - CW8 = 0x11, - CW9 = 0x12, - CW10 = 0x13, - CW11 = 0x14, - CW12 = 0x15, - CW13 = 0x16, - CW14 = 0x17, - CW15 = 0x18, -} - -/// Specifies an output channel of the AD9959 DDS chip. -pub enum Channel { - One = 0, - Two = 1, - Three = 2, - Four = 3, -} - -/// Possible errors generated by the AD9959 driver. -#[derive(Debug)] -pub enum Error { - Interface(InterfaceE), - Bounds, - Pin, - Frequency, -} - -impl From for Error { - fn from(interface_error: InterfaceE) -> Self { - Error::Interface(interface_error) - } -} - -impl Ad9959 -where - INTERFACE: Interface, - DELAY: DelayMs, - UPDATE: OutputPin, - -{ - pub fn new(interface: INTERFACE, - reset_pin: &mut RST, - io_update: UPDATE, - delay: DELAY, - desired_mode: Mode, - clock_frequency: u32, - multiplier: u8) -> Result> - where - RST: OutputPin, - { - let mut ad9959 = Ad9959 { - interface: interface, - io_update: io_update, - delay: delay, - reference_clock_frequency: clock_frequency, - system_clock_multiplier: 1, - }; - - ad9959.io_update.set_low().or_else(|_| Err(Error::Pin))?; - - // Reset the AD9959 - reset_pin.set_high().or_else(|_| Err(Error::Pin))?; - - // Delay for a clock cycle to allow the device to reset. - ad9959.delay.delay_ms((1000.0 / clock_frequency as f32) as u8); - - reset_pin.set_low().or_else(|_| Err(Error::Pin))?; - - ad9959.interface.configure_mode(Mode::SingleBitTwoWire)?; - - // Program the interface configuration in the AD9959. Default to all channels enabled. - let mut csr: [u8; 1] = [0xF0]; - csr[0].set_bits(1..3, desired_mode as u8); - ad9959.interface.write(0, &csr)?; - - // Configure the interface to the desired mode. - ad9959.interface.configure_mode(Mode::FourBitSerial)?; - - // Latch the configuration registers to make them active. - ad9959.latch_configuration()?; - - ad9959.interface.configure_mode(desired_mode)?; - - // Set the clock frequency to configure the device as necessary. - ad9959.configure_system_clock(clock_frequency, multiplier)?; - Ok(ad9959) - } - - fn latch_configuration(&mut self) -> Result<(), Error> { - self.io_update.set_high().or_else(|_| Err(Error::Pin))?; - // The SYNC_CLK is 1/4 the system clock frequency. The IO_UPDATE pin must be latched for one - // full SYNC_CLK pulse to register. For safety, we latch for 5 here. - self.delay.delay_ms((5000.0 / self.system_clock_frequency()) as u8); - self.io_update.set_low().or_else(|_| Err(Error::Pin))?; - - Ok(()) - } - - /// Configure the internal system clock of the chip. - /// - /// Arguments: - /// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core. - /// * `prescaler` - The frequency prescaler of the system clock. Must be 1 or 4-20. - /// - /// Returns: - /// The actual frequency configured for the internal system clock. - pub fn configure_system_clock(&mut self, - reference_clock_frequency: u32, - prescaler: u8) -> Result> - { - self.reference_clock_frequency = reference_clock_frequency; - - if prescaler != 1 && (prescaler > 20 || prescaler < 4) { - return Err(Error::Bounds); - } - - let frequency = prescaler as f64 * self.reference_clock_frequency as f64; - if frequency > 500_000_000.0f64 { - return Err(Error::Frequency); - } - - // TODO: Update / disable any enabled channels? - let mut fr1: [u8; 3] = [0, 0, 0]; - self.interface.read(Register::FR1 as u8, &mut fr1)?; - fr1[0].set_bits(2..=6, prescaler); - - let vco_range = frequency > 255e6; - fr1[0].set_bit(7, vco_range); - - self.interface.write(Register::FR1 as u8, &fr1)?; - self.system_clock_multiplier = prescaler; - - Ok(self.system_clock_frequency()) - } - - /// Perform a self-test of the communication interface. - /// - /// Note: - /// This modifies the existing channel enables. They are restored upon exit. - /// - /// Returns: - /// True if the self test succeeded. False otherwise. - pub fn self_test(&mut self) -> Result> { - let mut csr: [u8; 1] = [0]; - self.interface.read(Register::CSR as u8, &mut csr)?; - let old_csr = csr[0]; - - // Enable all channels. - csr[0].set_bits(4..8, 0xF); - self.interface.write(Register::CSR as u8, &csr)?; - - // Read back the enable. - csr[0] = 0; - self.interface.read(Register::CSR as u8, &mut csr)?; - if csr[0].get_bits(4..8) != 0xF { - return Ok(false); - } - - // Clear all channel enables. - csr[0].set_bits(4..8, 0x0); - self.interface.write(Register::CSR as u8, &csr)?; - - // Read back the enable. - csr[0] = 0xFF; - self.interface.read(Register::CSR as u8, &mut csr)?; - if csr[0].get_bits(4..8) != 0 { - return Ok(false); - } - - // Restore the CSR. - csr[0] = old_csr; - self.interface.write(Register::CSR as u8, &csr)?; - - Ok(true) - } - - fn system_clock_frequency(&self) -> f64 { - self.system_clock_multiplier as f64 * self.reference_clock_frequency as f64 - } - - /// Enable an output channel. - pub fn enable_channel(&mut self, channel: Channel) -> Result<(), Error> { - let mut csr: [u8; 1] = [0]; - self.interface.read(Register::CSR as u8, &mut csr)?; - csr[0].set_bit(channel as usize + 4, true); - self.interface.write(Register::CSR as u8, &csr)?; - - Ok(()) - } - - /// Disable an output channel. - pub fn disable_channel(&mut self, channel: Channel) -> Result<(), Error> { - let mut csr: [u8; 1] = [0]; - self.interface.read(Register::CSR as u8, &mut csr)?; - csr[0].set_bit(channel as usize + 4, false); - self.interface.write(Register::CSR as u8, &csr)?; - - Ok(()) - } - - fn modify_channel(&mut self, channel: Channel, register: Register, data: &[u8]) -> Result<(), Error> { - let mut csr: [u8; 1] = [0]; - self.interface.read(Register::CSR as u8, &mut csr)?; - - let mut new_csr = csr; - new_csr[0].set_bits(4..8, 0); - new_csr[0].set_bit(4 + channel as usize, true); - - self.interface.write(Register::CSR as u8, &new_csr)?; - - self.interface.write(register as u8, &data)?; - - // Latch the configuration and restore the previous CSR. Note that the re-enable of the - // channel happens immediately, so the CSR update does not need to be latched. - self.latch_configuration()?; - self.interface.write(Register::CSR as u8, &csr)?; - - Ok(()) - } - - /// Configure the phase of a specified channel. - /// - /// Arguments: - /// * `channel` - The channel to configure the frequency of. - /// * `phase_turns` - The desired phase offset in normalized turns. - /// - /// Returns: - /// The actual programmed phase offset of the channel in degrees. - pub fn set_phase(&mut self, channel: Channel, phase_turns: f32) -> Result> { - if phase_turns > 1.0 || phase_turns < 0.0 { - return Err(Error::Bounds); - } - - let phase_offset: u16 = (phase_turns * 1u32.wrapping_shl(14) as f32) as u16; - self.modify_channel(channel, Register::CPOW0, &phase_offset.to_be_bytes())?; - Ok((phase_offset as f32 / 1u32.wrapping_shl(14) as f32) * 360.0) - } - - /// Configure the amplitude of a specified channel. - /// - /// Arguments: - /// * `channel` - The channel to configure the frequency of. - /// * `amplitude` - A normalized amplitude setting [0, 1]. - /// - /// Returns: - /// The actual normalized amplitude of the channel relative to full-scale range. - pub fn set_amplitude(&mut self, channel: Channel, amplitude: f32) -> Result> { - if amplitude < 0.0 || amplitude > 1.0 { - return Err(Error::Bounds); - } - - let amplitude_control: u16 = (amplitude / 1u16.wrapping_shl(10) as f32) as u16; - let mut acr: [u8; 3] = [0, amplitude_control.to_be_bytes()[0], amplitude_control.to_be_bytes()[1]]; - - // Enable the amplitude multiplier for the channel if required. The amplitude control has - // full-scale at 0x3FF (amplitude of 1), so the multiplier should be disabled whenever - // full-scale is used. - acr[1].set_bit(4, amplitude_control >= 1u16.wrapping_shl(10)); - - self.modify_channel(channel, Register::ACR, &acr)?; - - Ok(amplitude_control as f32 / 1_u16.wrapping_shl(10) as f32) - } - - /// Configure the frequency of a specified channel. - /// - /// Arguments: - /// * `channel` - The channel to configure the frequency of. - /// * `frequency` - The desired output frequency in Hz. - /// - /// Returns: - /// The actual programmed frequency of the channel. - pub fn set_frequency(&mut self, channel: Channel, frequency: f64) -> Result> { - if frequency < 0.0 || frequency > self.system_clock_frequency() { - return Err(Error::Bounds); - } - - // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the - // frequency tuning word and f_s is the system clock rate. - let tuning_word: u32 = ((frequency as f64 / self.system_clock_frequency()) - * 1u64.wrapping_shl(32) as f64) as u32; - - self.modify_channel(channel, Register::CFTW0, &tuning_word.to_be_bytes())?; - Ok((tuning_word as f64 / 1u64.wrapping_shl(32) as f64) * self.system_clock_frequency()) - } -} diff --git a/stabilizer/Cargo.toml b/stabilizer/Cargo.toml index ffbd1e4..711476b 100644 --- a/stabilizer/Cargo.toml +++ b/stabilizer/Cargo.toml @@ -49,9 +49,6 @@ version = "0.6" features = ["ethernet", "proto-ipv4", "socket-tcp", "proto-ipv6"] default-features = false -[dependencies.ad9959] -path = "../ad9959" - [dependencies.stm32h7-ethernet] git = "https://github.com/quartiq/stm32h7-ethernet.git" features = ["stm32h743v"] diff --git a/stabilizer/src/main.rs b/stabilizer/src/main.rs index 1840360..1b42929 100644 --- a/stabilizer/src/main.rs +++ b/stabilizer/src/main.rs @@ -1,4 +1,4 @@ -//#![deny(warnings)] +#![deny(warnings)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -27,10 +27,7 @@ extern crate panic_halt; #[macro_use] extern crate log; -use nb; - // use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; -use asm_delay; use rtfm::cyccnt::{Instant, U32Ext}; use cortex_m_rt::exception; use cortex_m; @@ -51,7 +48,6 @@ use smoltcp as net; static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); mod eth; -mod pounder; mod server; mod afe; @@ -133,8 +129,6 @@ const APP: () = { _eth_mac: ethernet::EthernetMAC, mac_addr: net::wire::EthernetAddress, - //pounder: pounder::PounderDevices, - #[init([[0.; 5]; 2])] iir_state: [IIRState; 2], #[init([IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])] @@ -167,8 +161,6 @@ const APP: () = { clocks.rb.d2ccip1r.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); - let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks); - let gpioa = dp.GPIOA.split(&mut clocks.ahb4); let gpiob = dp.GPIOB.split(&mut clocks.ahb4); let gpioc = dp.GPIOC.split(&mut clocks.ahb4); @@ -282,88 +274,6 @@ const APP: () = { spi }; - // let pounder_devices = { - // let ad9959 = { - // let qspi_interface = { - // // Instantiate the QUADSPI pins and peripheral interface. - // // TODO: Place these into a pins structure that is provided to the QSPI - // // constructor. - // let _qspi_clk = gpiob.pb2.into_alternate_af9(); - // let _qspi_ncs = gpioc.pc11.into_alternate_af9(); - // let _qspi_io0 = gpioe.pe7.into_alternate_af10(); - // let _qspi_io1 = gpioe.pe8.into_alternate_af10(); - // let _qspi_io2 = gpioe.pe9.into_alternate_af10(); - // let _qspi_io3 = gpioe.pe10.into_alternate_af10(); - - // let qspi = hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()).unwrap(); - // pounder::QspiInterface::new(qspi).unwrap() - // }; - - // let mut reset_pin = gpioa.pa0.into_push_pull_output(); - // let io_update = gpiog.pg7.into_push_pull_output(); - - - // let asm_delay = { - // let frequency_hz = clocks.clocks.c_ck().0; - // asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz (frequency_hz)) - // }; - - // ad9959::Ad9959::new(qspi_interface, - // &mut reset_pin, - // io_update, - // asm_delay, - // ad9959::Mode::FourBitSerial, - // 100_000_000, - // 5).unwrap() - // }; - - // let io_expander = { - // let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); - // let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); - // let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks); - // mcp23017::MCP23017::default(i2c1).unwrap() - // }; - - // let spi = { - // let spi_mosi = gpiod.pd7.into_alternate_af5(); - // let spi_miso = gpioa.pa6.into_alternate_af5(); - // let spi_sck = gpiog.pg11.into_alternate_af5(); - - // let config = hal::spi::Config::new(hal::spi::Mode{ - // polarity: hal::spi::Polarity::IdleHigh, - // phase: hal::spi::Phase::CaptureOnSecondTransition, - // }) - // .frame_size(8); - - // dp.SPI1.spi((spi_sck, spi_miso, spi_mosi), config, 25.mhz(), &clocks) - // }; - - // let adc1 = { - // let mut adc = dp.ADC1.adc(&mut delay, &mut clocks); - // adc.calibrate(); - - // adc.enable() - // }; - - // let adc2 = { - // let mut adc = dp.ADC2.adc(&mut delay, &mut clocks); - // adc.calibrate(); - - // adc.enable() - // }; - - // let adc1_in_p = gpiof.pf11.into_analog(); - // let adc2_in_p = gpiof.pf14.into_analog(); - - // pounder::PounderDevices::new(io_expander, - // ad9959, - // spi, - // adc1, - // adc2, - // adc1_in_p, - // adc2_in_p).unwrap() - // }; - let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); let mut fp_led_1 = gpiod.pd6.into_push_pull_output(); let mut fp_led_2 = gpiod.pd12.into_push_pull_output(); @@ -470,7 +380,6 @@ const APP: () = { _afe2: afe2, timer: timer2, - //pounder: pounder_devices, eeprom_i2c: eeprom_i2c, net_interface: network_interface, diff --git a/stabilizer/src/pounder/attenuators.rs b/stabilizer/src/pounder/attenuators.rs deleted file mode 100644 index d9785f8..0000000 --- a/stabilizer/src/pounder/attenuators.rs +++ /dev/null @@ -1,57 +0,0 @@ -use super::error::Error; -use super::DdsChannel; - -pub trait AttenuatorInterface { - fn modify(&mut self, attenuation: f32, channel: DdsChannel) -> Result { - if attenuation > 31.5 || attenuation < 0.0 { - return Err(Error::Bounds); - } - - // Calculate the attenuation code to program into the attenuator. The attenuator uses a - // code where the LSB is 0.5 dB. - let attenuation_code = (attenuation * 2.0) as u8; - - // Read all the channels, modify the channel of interest, and write all the channels back. - // This ensures the staging register and the output register are always in sync. - let mut channels = [0_u8; 4]; - self.read_all(&mut channels)?; - - // The lowest 2 bits of the 8-bit shift register on the attenuator are ignored. Shift the - // attenuator code into the upper 6 bits of the register value. Note that the attenuator - // treats inputs as active-low, so the code is inverted before writing. - channels[channel as usize] = !attenuation_code.wrapping_shl(2); - self.write_all(&channels)?; - - // Finally, latch the output of the updated channel to force it into an active state. - self.latch(channel)?; - - Ok(attenuation_code as f32 / 2.0) - } - - fn read(&mut self, channel: DdsChannel) -> Result { - let mut channels = [0_u8; 4]; - - // Reading the data always shifts data out of the staging registers, so we perform a - // duplicate write-back to ensure the staging register is always equal to the output - // register. - self.read_all(&mut channels)?; - self.write_all(&channels)?; - - // The attenuation code is stored in the upper 6 bits of the register, where each LSB - // represents 0.5 dB. The attenuator stores the code as active-low, so inverting the result - // (before the shift) has the affect of transforming the bits of interest (and the - // dont-care bits) into an active-high state and then masking off the don't care bits. If - // the shift occurs before the inversion, the upper 2 bits (which would then be don't - // care) would contain erroneous data. - let attenuation_code = (!channels[channel as usize]).wrapping_shr(2); - - // Convert the desired channel code into dB of attenuation. - Ok(attenuation_code as f32 / 2.0) - } - - fn reset(&mut self) -> Result<(), Error>; - - fn latch(&mut self, channel: DdsChannel) -> Result<(), Error>; - fn read_all(&mut self, channels: &mut [u8; 4]) -> Result<(), Error>; - fn write_all(&mut self, channels: &[u8; 4]) -> Result<(), Error>; -} diff --git a/stabilizer/src/pounder/error.rs b/stabilizer/src/pounder/error.rs deleted file mode 100644 index b3cc596..0000000 --- a/stabilizer/src/pounder/error.rs +++ /dev/null @@ -1,11 +0,0 @@ -#[derive(Debug)] -pub enum Error { - Spi, - I2c, - DDS, - Qspi, - Bounds, - InvalidAddress, - InvalidChannel, - Adc, -} diff --git a/stabilizer/src/pounder/mod.rs b/stabilizer/src/pounder/mod.rs deleted file mode 100644 index d29e3bd..0000000 --- a/stabilizer/src/pounder/mod.rs +++ /dev/null @@ -1,265 +0,0 @@ -use mcp23017; -use ad9959; - -pub mod error; -pub mod attenuators; -mod rf_power; -pub mod types; - -use super::hal; - -use error::Error; -use attenuators::AttenuatorInterface; -use types::{DdsChannel, InputChannel}; -use rf_power::PowerMeasurementInterface; - -use embedded_hal::{ - blocking::spi::Transfer, - adc::OneShot -}; - -#[allow(dead_code)] -const OSC_EN_N_PIN: u8 = 8 + 7; - -const EXT_CLK_SEL_PIN: u8 = 8 + 6; - -const ATT_RST_N_PIN: u8 = 8 + 5; - -const ATT_LE0_PIN: u8 = 8 + 0; -const ATT_LE1_PIN: u8 = 8 + 1; -const ATT_LE2_PIN: u8 = 8 + 2; -const ATT_LE3_PIN: u8 = 8 + 3; - -pub struct QspiInterface { - pub qspi: hal::qspi::Qspi, - mode: ad9959::Mode, -} - -impl QspiInterface { - pub fn new(mut qspi: hal::qspi::Qspi) -> Result { - qspi.configure_mode(hal::qspi::QspiMode::FourBit).map_err(|_| Error::Qspi)?; - Ok(Self { qspi: qspi, mode: ad9959::Mode::SingleBitTwoWire }) - } -} - -impl ad9959::Interface for QspiInterface { - type Error = Error; - - fn configure_mode(&mut self, mode: ad9959::Mode) -> Result<(), Error> { - self.mode = mode; - - Ok(()) - } - - fn write(&mut self, addr: u8, data: &[u8]) -> Result<(), Error> { - if (addr & 0x80) != 0 { - return Err(Error::InvalidAddress); - } - - // The QSPI interface implementation always operates in 4-bit mode because the AD9959 uses - // IO3 as SYNC_IO in some output modes. In order for writes to be successful, SYNC_IO must - // be driven low. However, the QSPI peripheral forces IO3 high when operating in 1 or 2 bit - // modes. As a result, any writes while in single- or dual-bit modes has to instead write - // the data encoded into 4-bit QSPI data so that IO3 can be driven low. - match self.mode { - ad9959::Mode::SingleBitTwoWire => { - // Encode the data into a 4-bit QSPI pattern. - - // In 4-bit mode, we can send 2 bits of address and data per byte transfer. As - // such, we need at least 4x more bytes than the length of data. To avoid dynamic - // allocation, we assume the maximum transaction length for single-bit-two-wire is - // 2 bytes. - let mut encoded_data: [u8; 12] = [0; 12]; - - if (data.len() * 4) > (encoded_data.len() - 4) { - return Err(Error::Bounds); - } - - // Encode the address into the first 4 bytes. - for address_bit in 0..8 { - let offset: u8 = { - if address_bit % 2 == 0 { - 4 - } else { - 0 - } - }; - - if addr & address_bit != 0 { - encoded_data[(address_bit >> 1) as usize] |= 1 << offset; - } - } - - // Encode the data into the remaining bytes. - for byte_index in 0..data.len() { - let byte = data[byte_index]; - for address_bit in 0..8 { - let offset: u8 = { - if address_bit % 2 == 0 { - 4 - } else { - 0 - } - }; - - if byte & address_bit != 0 { - encoded_data[(byte_index + 1) * 4 + (address_bit >> 1) as usize] |= 1 << offset; - } - } - } - - let (encoded_address, encoded_payload) = { - let end_index = (1 + data.len()) * 4; - (encoded_data[0], &encoded_data[1..end_index]) - }; - - self.qspi.write(encoded_address, &encoded_payload).map_err(|_| Error::Qspi) - }, - ad9959::Mode::FourBitSerial => { - self.qspi.write(addr, &data).map_err(|_| Error::Qspi) - }, - _ => { - Err(Error::Qspi) - } - } - } - - fn read(&mut self, addr: u8, mut dest: &mut [u8]) -> Result<(), Error> { - if (addr & 0x80) != 0 { - return Err(Error::InvalidAddress); - } - - // It is not possible to read data from the AD9959 in single bit two wire mode because the - // QSPI interface assumes that data is always received on IO1. - if self.mode == ad9959::Mode::SingleBitTwoWire { - return Err(Error::Qspi); - } - - self.qspi.read(0x80_u8 | addr, &mut dest).map_err(|_| Error::Qspi) - } -} - -pub struct PounderDevices { - pub ad9959: ad9959::Ad9959>>, - mcp23017: mcp23017::MCP23017>, - attenuator_spi: hal::spi::Spi, - adc1: hal::adc::Adc, - adc2: hal::adc::Adc, - adc1_in_p: hal::gpio::gpiof::PF11, - adc2_in_p: hal::gpio::gpiof::PF14, -} - -impl PounderDevices -where - DELAY: embedded_hal::blocking::delay::DelayMs, -{ - pub fn new(mcp23017: mcp23017::MCP23017>, - ad9959: ad9959::Ad9959>>, - attenuator_spi: hal::spi::Spi, - adc1: hal::adc::Adc, - adc2: hal::adc::Adc, - adc1_in_p: hal::gpio::gpiof::PF11, - adc2_in_p: hal::gpio::gpiof::PF14, - ) -> Result { - let mut devices = Self { - mcp23017, - ad9959, - attenuator_spi, - adc1, - adc2, - adc1_in_p, - adc2_in_p, - }; - - // Configure power-on-default state for pounder. All LEDs are on, on-board oscillator - // selected, attenuators out of reset. - devices.mcp23017.write_gpio(mcp23017::Port::GPIOA, 0xF).map_err(|_| Error::I2c)?; - devices.mcp23017.write_gpio(mcp23017::Port::GPIOB, - 1_u8.wrapping_shl(5)).map_err(|_| Error::I2c)?; - devices.mcp23017.all_pin_mode(mcp23017::PinMode::OUTPUT).map_err(|_| Error::I2c)?; - - // Select the on-board clock with a 5x prescaler (500MHz). - devices.select_onboard_clock(5u8)?; - - Ok(devices) - } - - pub fn select_external_clock(&mut self, frequency: u32, prescaler: u8) -> Result<(), Error>{ - self.mcp23017.digital_write(EXT_CLK_SEL_PIN, true).map_err(|_| Error::I2c)?; - self.ad9959.configure_system_clock(frequency, prescaler).map_err(|_| Error::DDS)?; - - Ok(()) - } - - pub fn select_onboard_clock(&mut self, prescaler: u8) -> Result<(), Error> { - self.mcp23017.digital_write(EXT_CLK_SEL_PIN, false).map_err(|_| Error::I2c)?; - self.ad9959.configure_system_clock(100_000_000, prescaler).map_err(|_| Error::DDS)?; - - Ok(()) - } -} - -impl AttenuatorInterface for PounderDevices -{ - fn reset(&mut self) -> Result<(), Error> { - self.mcp23017.digital_write(ATT_RST_N_PIN, true).map_err(|_| Error::I2c)?; - // TODO: Measure the I2C transaction speed to the RST pin to ensure that the delay is - // sufficient. Document the delay here. - self.mcp23017.digital_write(ATT_RST_N_PIN, false).map_err(|_| Error::I2c)?; - - Ok(()) - } - - fn latch(&mut self, channel: DdsChannel) -> Result<(), Error> { - let pin = match channel { - DdsChannel::Zero => ATT_LE1_PIN, - DdsChannel::One => ATT_LE0_PIN, - DdsChannel::Two => ATT_LE3_PIN, - DdsChannel::Three => ATT_LE2_PIN, - }; - - self.mcp23017.digital_write(pin, true).map_err(|_| Error::I2c)?; - // TODO: Measure the I2C transaction speed to the RST pin to ensure that the delay is - // sufficient. Document the delay here. - self.mcp23017.digital_write(pin, false).map_err(|_| Error::I2c)?; - - Ok(()) - } - - fn read_all(&mut self, channels: &mut [u8; 4]) -> Result<(), Error> { - self.attenuator_spi.transfer(channels).map_err(|_| Error::Spi)?; - - Ok(()) - } - - fn write_all(&mut self, channels: &[u8; 4]) -> Result<(), Error> { - let mut result = [0_u8; 4]; - result.clone_from_slice(channels); - self.attenuator_spi.transfer(&mut result).map_err(|_| Error::Spi)?; - - Ok(()) - } -} - -impl PowerMeasurementInterface for PounderDevices { - fn sample_converter(&mut self, channel: InputChannel) -> Result { - let adc_scale = match channel { - InputChannel::Zero => { - let adc_reading: u32 = self.adc1.read(&mut self.adc1_in_p).map_err(|_| Error::Adc)?; - adc_reading as f32 / self.adc1.max_sample() as f32 - }, - InputChannel::One => { - let adc_reading: u32 = self.adc2.read(&mut self.adc2_in_p).map_err(|_| Error::Adc)?; - adc_reading as f32 / self.adc2.max_sample() as f32 - }, - }; - - // Convert analog percentage to voltage. - Ok(adc_scale * 3.3) - } -} diff --git a/stabilizer/src/pounder/rf_power.rs b/stabilizer/src/pounder/rf_power.rs deleted file mode 100644 index dd7a3ec..0000000 --- a/stabilizer/src/pounder/rf_power.rs +++ /dev/null @@ -1,14 +0,0 @@ -use super::Error; -use super::InputChannel; - -pub trait PowerMeasurementInterface { - fn sample_converter(&mut self, channel: InputChannel) -> Result; - - fn measure_power(&mut self, channel: InputChannel) -> Result { - let analog_measurement = self.sample_converter(channel)?; - - // The AD8363 with VSET connected to VOUT provides an output voltage of 51.7mV / dB at - // 100MHz. - Ok(analog_measurement / 0.0517) - } -} diff --git a/stabilizer/src/pounder/types.rs b/stabilizer/src/pounder/types.rs deleted file mode 100644 index 9938bfe..0000000 --- a/stabilizer/src/pounder/types.rs +++ /dev/null @@ -1,16 +0,0 @@ - -#[allow(dead_code)] -#[derive(Debug, Copy, Clone)] -pub enum DdsChannel { - Zero, - One, - Two, - Three, -} - -#[allow(dead_code)] -#[derive(Debug, Copy, Clone)] -pub enum InputChannel { - Zero, - One, -} From 547fe1bd40b010440478eafd0d09f538c9aaaa36 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 8 Jun 2020 18:36:29 +0200 Subject: [PATCH 6/7] Removing ethernet module --- stabilizer/src/eth.rs | 605 ----------------------------------------- stabilizer/src/main.rs | 4 +- 2 files changed, 1 insertion(+), 608 deletions(-) delete mode 100644 stabilizer/src/eth.rs diff --git a/stabilizer/src/eth.rs b/stabilizer/src/eth.rs deleted file mode 100644 index 267a098..0000000 --- a/stabilizer/src/eth.rs +++ /dev/null @@ -1,605 +0,0 @@ -use core::{cmp, slice}; -use smoltcp::phy; -use smoltcp::time::Instant; -use smoltcp::wire::EthernetAddress; -use smoltcp::Result; -use super::{pac}; - -#[allow(dead_code)] -mod phy_consts { - pub const PHY_REG_BCR: u8 = 0x00; - pub const PHY_REG_BSR: u8 = 0x01; - pub const PHY_REG_ID1: u8 = 0x02; - pub const PHY_REG_ID2: u8 = 0x03; - pub const PHY_REG_ANTX: u8 = 0x04; - pub const PHY_REG_ANRX: u8 = 0x05; - pub const PHY_REG_ANEXP: u8 = 0x06; - pub const PHY_REG_ANNPTX: u8 = 0x07; - pub const PHY_REG_ANNPRX: u8 = 0x08; - pub const PHY_REG_SSR: u8 = 0x1F; // Special Status Register - pub const PHY_REG_CTL: u8 = 0x0D; // Ethernet PHY Register Control - pub const PHY_REG_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data - - pub const PHY_REG_WUCSR: u16 = 0x8010; - - pub const PHY_REG_BCR_COLTEST: u16 = 1 << 7; - pub const PHY_REG_BCR_FD: u16 = 1 << 8; - pub const PHY_REG_BCR_ANRST: u16 = 1 << 9; - pub const PHY_REG_BCR_ISOLATE: u16 = 1 << 10; - pub const PHY_REG_BCR_POWERDN: u16 = 1 << 11; - pub const PHY_REG_BCR_AN: u16 = 1 << 12; - pub const PHY_REG_BCR_100M: u16 = 1 << 13; - pub const PHY_REG_BCR_LOOPBACK: u16 = 1 << 14; - pub const PHY_REG_BCR_RESET: u16 = 1 << 15; - - pub const PHY_REG_BSR_JABBER: u16 = 1 << 1; - pub const PHY_REG_BSR_UP: u16 = 1 << 2; - pub const PHY_REG_BSR_FAULT: u16 = 1 << 4; - pub const PHY_REG_BSR_ANDONE: u16 = 1 << 5; - - pub const PHY_REG_SSR_ANDONE: u16 = 1 << 12; - pub const PHY_REG_SSR_SPEED: u16 = 0b111 << 2; - pub const PHY_REG_SSR_10BASE_HD: u16 = 0b001 << 2; - pub const PHY_REG_SSR_10BASE_FD: u16 = 0b101 << 2; - pub const PHY_REG_SSR_100BASE_HD: u16 = 0b010 << 2; - pub const PHY_REG_SSR_100BASE_FD: u16 = 0b110 << 2; -} -use self::phy_consts::*; - -const EMAC_DES3_OWN: u32 = 0x8000_0000; -const EMAC_DES3_CTXT: u32 = 0x4000_0000; -const EMAC_DES3_FD: u32 = 0x2000_0000; -const EMAC_DES3_LD: u32 = 0x1000_0000; -const EMAC_DES3_ES: u32 = 0x0000_8000; -const EMAC_TDES2_IOC: u32 = 0x8000_0000; -const EMAC_RDES3_IOC: u32 = 0x4000_0000; -const EMAC_RDES3_PL: u32 = 0x0000_7FFF; -const EMAC_RDES3_BUF1V: u32 = 0x0100_0000; -const EMAC_TDES2_B1L: u32 = 0x0000_3FFF; -const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF; - -// 6 DMAC, 6 SMAC, 4 q tag, 2 ethernet type II, 1500 ip MTU, 4 CRC, 2 padding -const ETH_BUFFER_SIZE: usize = 1524; -const ETH_DESC_U32_SIZE: usize = 4; -const ETH_TX_BUFFER_COUNT: usize = 4; -const ETH_RX_BUFFER_COUNT: usize = 4; - -#[allow(dead_code)] -mod cr_consts { - /* For HCLK 60-100 MHz */ - pub const ETH_MACMIIAR_CR_HCLK_DIV_42: u8 = 0; - /* For HCLK 100-150 MHz */ - pub const ETH_MACMIIAR_CR_HCLK_DIV_62: u8 = 1; - /* For HCLK 20-35 MHz */ - pub const ETH_MACMIIAR_CR_HCLK_DIV_16: u8 = 2; - /* For HCLK 35-60 MHz */ - pub const ETH_MACMIIAR_CR_HCLK_DIV_26: u8 = 3; - /* For HCLK 150-250 MHz */ - pub const ETH_MACMIIAR_CR_HCLK_DIV_102: u8 = 4; - /* For HCLK 250-300 MHz */ - pub const ETH_MACMIIAR_CR_HCLK_DIV_124: u8 = 5; -} -use self::cr_consts::*; - -// set clock range in MAC MII address register -// 200 MHz AHB clock = eth_hclk -const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102; - -const PHY_ADDR: u8 = 0; - -fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 { - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdioar.modify(|_, w| unsafe { - w.pa() - .bits(PHY_ADDR) - .rda() - .bits(reg_addr) - .goc() - .bits(0b11) // read - .cr() - .bits(CLOCK_RANGE) - .mb() - .set_bit() - }); - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdiodr.read().md().bits() -} - -fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) { - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); - mac.macmdioar.modify(|_, w| unsafe { - w.pa() - .bits(PHY_ADDR) - .rda() - .bits(reg_addr) - .goc() - .bits(0b01) // write - .cr() - .bits(CLOCK_RANGE) - .mb() - .set_bit() - }); - while mac.macmdioar.read().mb().bit_is_set() {} -} - -// Writes a value to an extended PHY register in MMD address space -fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) { - phy_write(PHY_REG_CTL, 0x0003, mac); // set address - phy_write(PHY_REG_ADDAR, reg_addr, mac); - phy_write(PHY_REG_CTL, 0x4003, mac); // set data - phy_write(PHY_REG_ADDAR, reg_data, mac); -} - -#[repr(align(4))] -struct RxRing { - desc_buf: [[u32; ETH_DESC_U32_SIZE]; ETH_RX_BUFFER_COUNT], - pkt_buf: [[u8; ETH_BUFFER_SIZE]; ETH_RX_BUFFER_COUNT], - cur_desc: usize, -} - -impl RxRing { - const fn new() -> Self { - Self { - desc_buf: [[0; ETH_DESC_U32_SIZE]; ETH_RX_BUFFER_COUNT], - pkt_buf: [[0; ETH_BUFFER_SIZE]; ETH_RX_BUFFER_COUNT], - cur_desc: 0, - } - } - - unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) { - assert_eq!(self.desc_buf[0].len() % 4, 0); - assert_eq!(self.pkt_buf[0].len() % 4, 0); - - for i in 0..self.desc_buf.len() { - for j in 0..self.desc_buf[0].len() { - self.desc_buf[i][j] = 0; - } - for j in 0..self.pkt_buf[0].len() { - self.pkt_buf[i][j] = 0; - } - } - - let addr = &self.desc_buf as *const _ as u32; - assert_eq!(addr & 0x3, 0); - dma.dmacrx_dlar.write(|w| w.bits(addr)); - dma.dmacrx_rlr - .write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1)); - - self.cur_desc = 0; - for _ in 0..self.desc_buf.len() { - self.buf_release() - } - } - - fn next_desc(&self) -> usize { - (self.cur_desc + 1) % self.desc_buf.len() - } - - // not owned by DMA - fn buf_owned(&self) -> bool { - self.desc_buf[self.cur_desc][3] & EMAC_DES3_OWN == 0 - } - - fn buf_valid(&self) -> bool { - self.desc_buf[self.cur_desc][3] - & (EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_ES | EMAC_DES3_CTXT) - == (EMAC_DES3_FD | EMAC_DES3_LD) - } - - unsafe fn buf_as_slice_mut<'a>(&self) -> &'a mut [u8] { - let len = (self.desc_buf[self.cur_desc][3] & EMAC_RDES3_PL) as usize; - let len = cmp::min(len, ETH_BUFFER_SIZE); - let addr = &self.pkt_buf[self.cur_desc] as *const _ as *mut u8; - slice::from_raw_parts_mut(addr, len) - } - - fn buf_release(&mut self) { - let addr = &self.pkt_buf[self.cur_desc] as *const _; - self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP; - self.desc_buf[self.cur_desc][3] = - EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN; - - let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; - assert_eq!(addr & 0x3, 0); - - let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA }; - - // Ensure changes to the descriptor (in particular, the OWN flag) are - // committed before DMA engine sees tail pointer store. - cortex_m::asm::dsb(); - - dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) }); - - self.cur_desc = self.next_desc(); - } -} - -#[repr(align(4))] -struct TxRing { - desc_buf: [[u32; ETH_DESC_U32_SIZE]; ETH_TX_BUFFER_COUNT], - pkt_buf: [[u8; ETH_BUFFER_SIZE]; ETH_TX_BUFFER_COUNT], - cur_desc: usize, -} - -impl TxRing { - const fn new() -> Self { - Self { - desc_buf: [[0; ETH_DESC_U32_SIZE]; ETH_TX_BUFFER_COUNT], - pkt_buf: [[0; ETH_BUFFER_SIZE]; ETH_TX_BUFFER_COUNT], - cur_desc: 0, - } - } - - unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) { - assert_eq!(self.desc_buf[0].len() % 4, 0); - assert_eq!(self.pkt_buf[0].len() % 4, 0); - - for i in 0..self.desc_buf.len() { - for j in 0..self.desc_buf[0].len() { - self.desc_buf[i][j] = 0; - } - for j in 0..self.pkt_buf[0].len() { - self.pkt_buf[i][j] = 0; - } - } - self.cur_desc = 0; - - let addr = &self.desc_buf as *const _ as u32; - assert_eq!(addr & 0x3, 0); - dma.dmactx_dlar.write(|w| w.bits(addr)); - dma.dmactx_rlr - .write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1)); - let addr = &self.desc_buf[0] as *const _ as u32; - assert_eq!(addr & 0x3, 0); - dma.dmactx_dtpr.write(|w| w.bits(addr)); - } - - fn next_desc(&self) -> usize { - (self.cur_desc + 1) % self.desc_buf.len() - } - - // not owned by DMA - fn buf_owned(&self) -> bool { - self.desc_buf[self.cur_desc][3] & EMAC_DES3_OWN == 0 - } - - unsafe fn buf_as_slice_mut<'a>(&mut self, len: usize) -> &'a mut [u8] { - let len = cmp::min(len, ETH_BUFFER_SIZE); - self.desc_buf[self.cur_desc][2] = - EMAC_TDES2_IOC | (len as u32 & EMAC_TDES2_B1L); - let addr = &self.pkt_buf[self.cur_desc] as *const _ as *mut u8; - self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP; - slice::from_raw_parts_mut(addr, len) - } - - fn buf_release(&mut self) { - self.desc_buf[self.cur_desc][3] = - EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD; - self.cur_desc = self.next_desc(); - - let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; - assert_eq!(addr & 0x3, 0); - - let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA }; - - // Ensure packet contents as well as changes to the descriptor have been - // committed before DMA engine sees the tail pointer store. - cortex_m::asm::dsb(); - - dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) }); - } -} - -pub struct Device { - rx: RxRing, - tx: TxRing, -} - -impl Device { - pub const fn new() -> Self { - Self { - rx: RxRing::new(), - tx: TxRing::new(), - } - } - - // Initialize the ethernet peripherals - // - // # Safety - // - // This iis transitively unsafe since it sets potentially - // unsafe register values. Might ultimately be safe if the values - // are correct. - // - // After `init` is called, `Device` shall not be moved. - pub unsafe fn init( - &mut self, - mac: EthernetAddress, - eth_mac: &pac::ETHERNET_MAC, - eth_dma: &pac::ETHERNET_DMA, - eth_mtl: &pac::ETHERNET_MTL, - ) { - eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); - while eth_dma.dmamr.read().swr().bit_is_set() {} - - // 200 MHz - eth_mac - .mac1ustcr - .modify(|_, w| w.tic_1us_cntr().bits(200 - 1)); - - // Configuration Register - eth_mac.maccr.modify(|_, w| { - w.arpen() - .clear_bit() - .ipc() - .set_bit() - .ipg() - .bits(0b000) // 96 bit - .ecrsfd() - .clear_bit() - .dcrs() - .clear_bit() - .bl() - .bits(0b00) // 19 - .prelen() - .bits(0b00) // 7 - // CRC stripping for Type frames - .cst() - .set_bit() - // Fast Ethernet speed - .fes() - .set_bit() - // Duplex mode - .dm() - .set_bit() - // Automatic pad/CRC stripping - .acs() - .set_bit() - // Retry disable in half-duplex mode - .dr() - .set_bit() - }); - eth_mac.macecr.modify(|_, w| { - w.eipgen() - .clear_bit() - .usp() - .clear_bit() - .spen() - .clear_bit() - .dcrcc() - .clear_bit() - }); - // Set the MAC address - eth_mac.maca0lr.write(|w| { - w.addrlo().bits( - u32::from(mac.0[0]) - | (u32::from(mac.0[1]) << 8) - | (u32::from(mac.0[2]) << 16) - | (u32::from(mac.0[3]) << 24), - ) - }); - eth_mac.maca0hr.write(|w| { - w.addrhi() - .bits(u16::from(mac.0[4]) | (u16::from(mac.0[5]) << 8)) - }); - // frame filter register - eth_mac.macpfr.modify(|_, w| { - w.dntu() - .clear_bit() - .ipfe() - .clear_bit() - .vtfe() - .clear_bit() - .hpf() - .clear_bit() - .saf() - .clear_bit() - .saif() - .clear_bit() - .pcf() - .bits(0b00) - .dbf() - .clear_bit() - .pm() - .clear_bit() - .daif() - .clear_bit() - .hmc() - .clear_bit() - .huc() - .clear_bit() - // Receive All - .ra() - .clear_bit() - // Promiscuous mode - .pr() - .clear_bit() - }); - eth_mac.macwtr.write(|w| w.pwe().clear_bit()); - // Flow Control Register - eth_mac.macqtx_fcr.modify(|_, w| { - // Pause time - w.pt().bits(0x100) - }); - eth_mac.macrx_fcr.modify(|_, w| w); - eth_mtl.mtlrx_qomr.modify(|_, w| { - w - // Receive store and forward - .rsf() - .set_bit() - // Dropping of TCP/IP checksum error frames disable - .dis_tcp_ef() - .clear_bit() - // Forward error frames - .fep() - .clear_bit() - // Forward undersized good packets - .fup() - .clear_bit() - }); - eth_mtl.mtltx_qomr.modify(|_, w| { - w - // Transmit store and forward - .tsf() - .set_bit() - }); - - if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007) - | (phy_read(PHY_REG_ID2, eth_mac) != 0xC131) - { - error!("PHY ID error!"); - } - - phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac); - while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET - == PHY_REG_BCR_RESET - {} - phy_write_ext(PHY_REG_WUCSR, 0, eth_mac); - phy_write( - PHY_REG_BCR, - PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M, - eth_mac, - ); - /* - while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {}; - while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {}; - while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED) - != PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {}; - */ - - // operation mode register - eth_dma.dmamr.modify(|_, w| { - w.intm() - .bits(0b00) - // Rx Tx priority ratio 1:1 - .pr() - .bits(0b000) - .txpr() - .clear_bit() - .da() - .clear_bit() - }); - // bus mode register - eth_dma.dmasbmr.modify(|_, w| { - // Address-aligned beats - w.aal() - .set_bit() - // Fixed burst - .fb() - .set_bit() - }); - eth_dma - .dmaccr - .modify(|_, w| w.dsl().bits(0).pblx8().clear_bit().mss().bits(536)); - eth_dma.dmactx_cr.modify(|_, w| { - w - // Tx DMA PBL - .txpbl() - .bits(32) - .tse() - .clear_bit() - // Operate on second frame - .osf() - .clear_bit() - }); - - eth_dma.dmacrx_cr.modify(|_, w| { - w - // receive buffer size - .rbsz() - .bits(ETH_BUFFER_SIZE as u16) - // Rx DMA PBL - .rxpbl() - .bits(32) - // Disable flushing of received frames - .rpf() - .clear_bit() - }); - - self.rx.init(eth_dma); - self.tx.init(eth_dma); - - // Manage MAC transmission and reception - eth_mac.maccr.modify(|_, w| { - w.re() - .bit(true) // Receiver Enable - .te() - .bit(true) // Transmiter Enable - }); - eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit()); - - // Ensure ring buffer descriptors have been set up in memory before - // enabling DMA engine. - cortex_m::asm::dsb(); - - // Manage DMA transmission and reception - eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); - eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit()); - - eth_dma - .dmacsr - .modify(|_, w| w.tps().set_bit().rps().set_bit()); - } -} - -impl<'a, 'b> phy::Device<'a> for &'b mut Device { - type RxToken = RxToken<'a>; - type TxToken = TxToken<'a>; - - fn capabilities(&self) -> phy::DeviceCapabilities { - let mut capabilities = phy::DeviceCapabilities::default(); - // ethernet frame type II (6 smac, 6 dmac, 2 ethertype), - // sans CRC (4), 1500 IP MTU - capabilities.max_transmission_unit = 1514; - capabilities.max_burst_size = Some(self.tx.desc_buf.len()); - capabilities - } - - fn receive(&mut self) -> Option<(RxToken, TxToken)> { - // Skip all queued packets with errors. - while self.rx.buf_owned() && !self.rx.buf_valid() { - self.rx.buf_release() - } - - if !(self.rx.buf_owned() && self.tx.buf_owned()) { - return None; - } - - Some((RxToken(&mut self.rx), TxToken(&mut self.tx))) - } - - fn transmit(&mut self) -> Option { - if !self.tx.buf_owned() { - return None; - } - - Some(TxToken(&mut self.tx)) - } -} - -pub struct RxToken<'a>(&'a mut RxRing); - -impl<'a> phy::RxToken for RxToken<'a> { - fn consume(self, _timestamp: Instant, f: F) -> Result - where - F: FnOnce(&mut [u8]) -> Result, - { - let result = f(unsafe { self.0.buf_as_slice_mut() }); - self.0.buf_release(); - result - } -} - -pub struct TxToken<'a>(&'a mut TxRing); - -impl<'a> phy::TxToken for TxToken<'a> { - fn consume(self, _timestamp: Instant, len: usize, f: F) -> Result - where - F: FnOnce(&mut [u8]) -> Result, - { - let result = f(unsafe { self.0.buf_as_slice_mut(len) }); - self.0.buf_release(); - result - } -} diff --git a/stabilizer/src/main.rs b/stabilizer/src/main.rs index 1b42929..5aef04b 100644 --- a/stabilizer/src/main.rs +++ b/stabilizer/src/main.rs @@ -11,7 +11,7 @@ #[panic_handler] #[cfg(all(feature = "nightly", not(feature = "semihosting")))] fn panic(_info: &core::panic::PanicInfo) -> ! { - let gpiod = unsafe { &*pac::GPIOD::ptr() }; + let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() }; gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3 unsafe { core::intrinsics::abort(); @@ -34,7 +34,6 @@ use cortex_m; use stm32h7xx_hal as hal; use stm32h7xx_hal::{ prelude::*, - stm32 as pac, }; use embedded_hal::{ @@ -47,7 +46,6 @@ use smoltcp as net; #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); -mod eth; mod server; mod afe; From 7fefb4c61261aacfd4794cb2140843b98571e929 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 8 Jun 2020 18:53:07 +0200 Subject: [PATCH 7/7] Simplifying GPIO API --- stabilizer/src/main.rs | 14 +++++++------- stm32h7xx-hal | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/stabilizer/src/main.rs b/stabilizer/src/main.rs index 5aef04b..4a7b69e 100644 --- a/stabilizer/src/main.rs +++ b/stabilizer/src/main.rs @@ -159,13 +159,13 @@ const APP: () = { clocks.rb.d2ccip1r.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); - let gpioa = dp.GPIOA.split(&mut clocks.ahb4); - let gpiob = dp.GPIOB.split(&mut clocks.ahb4); - let gpioc = dp.GPIOC.split(&mut clocks.ahb4); - let gpiod = dp.GPIOD.split(&mut clocks.ahb4); - let gpioe = dp.GPIOE.split(&mut clocks.ahb4); - let gpiof = dp.GPIOF.split(&mut clocks.ahb4); - let gpiog = dp.GPIOG.split(&mut clocks.ahb4); + let gpioa = dp.GPIOA.split(&mut clocks); + let gpiob = dp.GPIOB.split(&mut clocks); + let gpioc = dp.GPIOC.split(&mut clocks); + let gpiod = dp.GPIOD.split(&mut clocks); + let gpioe = dp.GPIOE.split(&mut clocks); + let gpiof = dp.GPIOF.split(&mut clocks); + let gpiog = dp.GPIOG.split(&mut clocks); let afe1 = { let a0_pin = gpiof.pf2.into_push_pull_output(); diff --git a/stm32h7xx-hal b/stm32h7xx-hal index 2236b57..d79cb00 160000 --- a/stm32h7xx-hal +++ b/stm32h7xx-hal @@ -1 +1 @@ -Subproject commit 2236b578b48aa195679dd65515f595f491f88513 +Subproject commit d79cb0015a6f0cbb819907efe3a817f7dce14bab