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new file mode 100644
index 0000000..5340aad
--- /dev/null
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- "bitflags 1.2.1 (registry+https://github.com/rust-lang/crates.io-index)",
- "byteorder 1.3.4 (registry+https://github.com/rust-lang/crates.io-index)",
- "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
- "managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)",
+ "bitflags",
+ "byteorder",
+ "log",
+ "managed",
 ]
 
 [[package]]
 name = "stabilizer"
 version = "0.3.0"
 dependencies = [
- "ad9959 0.1.0 (git+https://github.com/quartiq/ad9959.git?branch=feature/basic-driver)",
- "asm-delay 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m 0.6.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-log 0.6.1 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-rt 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-rtfm 0.5.1 (registry+https://github.com/rust-lang/crates.io-index)",
- "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "heapless 0.5.5 (registry+https://github.com/rust-lang/crates.io-index)",
- "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
- "mcp23017 0.1.1 (git+https://github.com/mrd0ll4r/mcp23017.git)",
- "nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "panic-halt 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "panic-semihosting 0.5.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "serde 1.0.111 (registry+https://github.com/rust-lang/crates.io-index)",
- "serde-json-core 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "stm32h7-ethernet 0.1.1 (git+https://github.com/quartiq/stm32h7-ethernet.git)",
+ "asm-delay",
+ "cortex-m",
+ "cortex-m-log",
+ "cortex-m-rt",
+ "cortex-m-rtfm",
+ "embedded-hal",
+ "enum-iterator",
+ "heapless",
+ "log",
+ "mcp23017",
+ "nb",
+ "panic-halt",
+ "panic-semihosting",
+ "serde",
+ "serde-json-core",
+ "smoltcp",
+ "stm32h7-ethernet",
  "stm32h7xx-hal 0.5.0",
 ]
 
@@ -410,16 +452,18 @@ dependencies = [
 name = "stable_deref_trait"
 version = "1.1.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
 
 [[package]]
 name = "stm32h7"
 version = "0.11.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e9beb5e2a223c82f263c3051bba4614aebc6e98bd40217df3cd8817c83ac7bd8"
 dependencies = [
- "bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m 0.6.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-rt 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)",
- "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
+ "bare-metal",
+ "cortex-m",
+ "cortex-m-rt",
+ "vcell",
 ]
 
 [[package]]
@@ -427,9 +471,9 @@ name = "stm32h7-ethernet"
 version = "0.1.1"
 source = "git+https://github.com/quartiq/stm32h7-ethernet.git#cf9b8bb2e1b440d8ada6ac6048f48dc4ed9c269a"
 dependencies = [
- "cortex-m 0.6.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
- "smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
+ "cortex-m",
+ "log",
+ "smoltcp",
  "stm32h7xx-hal 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)",
 ]
 
@@ -437,127 +481,77 @@ dependencies = [
 name = "stm32h7xx-hal"
 version = "0.5.0"
 dependencies = [
- "bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)",
- "cast 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m 0.6.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-rt 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)",
- "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "paste 0.1.16 (registry+https://github.com/rust-lang/crates.io-index)",
- "stm32h7 0.11.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)",
+ "bare-metal",
+ "cast",
+ "cortex-m",
+ "cortex-m-log",
+ "cortex-m-rt",
+ "cortex-m-rtfm",
+ "embedded-hal",
+ "nb",
+ "panic-itm",
+ "paste",
+ "stm32h7",
+ "void",
 ]
 
 [[package]]
 name = "stm32h7xx-hal"
 version = "0.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "987c66628f30012ed9a41cc738421c5caece03292c0cc8fd1e99956f122735bd"
 dependencies = [
- "bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)",
- "cast 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m 0.6.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-rt 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)",
- "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "paste 0.1.16 (registry+https://github.com/rust-lang/crates.io-index)",
- "stm32h7 0.11.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)",
+ "bare-metal",
+ "cast",
+ "cortex-m",
+ "cortex-m-rt",
+ "embedded-hal",
+ "nb",
+ "paste",
+ "stm32h7",
+ "void",
 ]
 
 [[package]]
 name = "syn"
 version = "1.0.30"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "93a56fabc59dce20fe48b6c832cc249c713e7ed88fa28b0ee0a3bfcaae5fe4e2"
 dependencies = [
- "proc-macro2 1.0.18 (registry+https://github.com/rust-lang/crates.io-index)",
- "quote 1.0.6 (registry+https://github.com/rust-lang/crates.io-index)",
- "unicode-xid 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
+ "proc-macro2",
+ "quote",
+ "unicode-xid",
 ]
 
 [[package]]
 name = "typenum"
 version = "1.12.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "373c8a200f9e67a0c95e62a4f52fbf80c23b4381c05a17845531982fa99e6b33"
 
 [[package]]
 name = "unicode-xid"
 version = "0.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "826e7639553986605ec5979c7dd957c7895e93eabed50ab2ffa7f6128a75097c"
 
 [[package]]
 name = "vcell"
 version = "0.1.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "876e32dcadfe563a4289e994f7cb391197f362b6315dc45e8ba4aa6f564a4b3c"
 
 [[package]]
 name = "void"
 version = "1.0.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
 
 [[package]]
 name = "volatile-register"
 version = "0.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0d67cb4616d99b940db1d6bd28844ff97108b498a6ca850e5b6191a532063286"
 dependencies = [
- "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
+ "vcell",
 ]
-
-[metadata]
-"checksum ad9959 0.1.0 (git+https://github.com/quartiq/ad9959.git?branch=feature/basic-driver)" = "<none>"
-"checksum aligned 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "d39da9b88ae1a81c03c9c082b8db83f1d0e93914126041962af61034ab44c4a5"
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-"checksum mcp23017 0.1.1 (git+https://github.com/mrd0ll4r/mcp23017.git)" = "<none>"
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-"checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
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-"checksum serde-json-core 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "cbf406405ada9ef326ca78677324ac66994ff348fc48a16030be08caeed29825"
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diff --git a/Cargo.toml b/Cargo.toml
index 31e0403..ac00002 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,72 +1,10 @@
-[package]
-name = "stabilizer"
-version = "0.3.0"
-authors = ["Robert Jördens <rj@quartiq.de>"]
-description = "Firmware for the Sinara Stabilizer board (stm32h743, eth, poe, 2 adc, 2 dac)"
-categories = ["embedded", "no-std", "hardware-support", "science"]
-license = "GPL-3.0-or-later"
-keywords = ["ethernet", "stm32h7", "adc", "dac", "physics"]
-repository = "https://github.com/quartiq/stabilizer"
-readme = "README.md"
-documentation = "https://docs.rs/stabilizer/"
-edition = "2018"
-exclude = [
-	".travis.yml",
-	".gitignore",
-	"doc/",
-	"doc/*"
+[workspace]
+
+members = [
+    "stabilizer",
+    "stm32h7xx-hal",
 ]
 
-[badges]
-travis-ci = { repository = "quartiq/stabilizer", branch = "master" }
-maintenance = { status = "experimental" }
-
-[package.metadata.docs.rs]
-features = []
-default-target = "thumbv7em-none-eabihf"
-
-[dependencies]
-cortex-m = { version = "0.6", features = ["const-fn"] }
-cortex-m-rt = { version = "0.6", features = ["device"] }
-cortex-m-log = { version = "0.6", features = ["log-integration"] }
-log = "0.4"
-panic-semihosting = { version = "0.5", optional = true }
-panic-halt = "0.2"
-serde = { version = "1.0", features = ["derive"], default-features = false }
-heapless = { version = "0.5.4", features = ["serde"] }
-serde-json-core = "0.1"
-cortex-m-rtfm = "0.5"
-embedded-hal = "0.2.3"
-nb = "0.1.2"
-asm-delay = "0.7.0"
-
-[dependencies.mcp23017]
-git = "https://github.com/mrd0ll4r/mcp23017.git"
-
-[dependencies.smoltcp]
-version = "0.6"
-features = ["ethernet", "proto-ipv4", "socket-tcp", "proto-ipv6"]
-default-features = false
-
-[dependencies.ad9959]
-git = "https://github.com/quartiq/ad9959.git"
-branch = "feature/basic-driver"
-
-[dependencies.stm32h7-ethernet]
-git = "https://github.com/quartiq/stm32h7-ethernet.git"
-features = ["stm32h743v"]
-
-[dependencies.stm32h7xx-hal]
-#git = "https://github.com/quartiq/stm32h7xx-hal.git"
-#branch = "feature/quad-spi"
-path = "../stm32h7xx-hal/"
-features = ["stm32h743v", "rt", "unproven"]
-
-[features]
-semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
-bkpt = [ ]
-nightly = ["cortex-m/inline-asm"]
-
 [profile.dev]
 codegen-units = 1
 incremental = false
diff --git a/openocd.gdb b/openocd.gdb
index 1728d7e..e903a33 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -16,7 +16,7 @@ break rust_begin_unwind
 
 load
 # tbreak cortex_m_rt::reset_handler
-# monitor reset halt
+monitor reset halt
 
 # cycle counter delta tool, place two bkpts around the section
 set var $cc=0xe0001004
@@ -26,4 +26,3 @@ set var $t0=*$cc
 continue
 end
 #set var $t0=*$cc
-continue
diff --git a/src/eth.rs b/src/eth.rs
deleted file mode 100644
index 267a098..0000000
--- a/src/eth.rs
+++ /dev/null
@@ -1,605 +0,0 @@
-use core::{cmp, slice};
-use smoltcp::phy;
-use smoltcp::time::Instant;
-use smoltcp::wire::EthernetAddress;
-use smoltcp::Result;
-use super::{pac};
-
-#[allow(dead_code)]
-mod phy_consts {
-    pub const PHY_REG_BCR: u8 = 0x00;
-    pub const PHY_REG_BSR: u8 = 0x01;
-    pub const PHY_REG_ID1: u8 = 0x02;
-    pub const PHY_REG_ID2: u8 = 0x03;
-    pub const PHY_REG_ANTX: u8 = 0x04;
-    pub const PHY_REG_ANRX: u8 = 0x05;
-    pub const PHY_REG_ANEXP: u8 = 0x06;
-    pub const PHY_REG_ANNPTX: u8 = 0x07;
-    pub const PHY_REG_ANNPRX: u8 = 0x08;
-    pub const PHY_REG_SSR: u8 = 0x1F; // Special Status Register
-    pub const PHY_REG_CTL: u8 = 0x0D; // Ethernet PHY Register Control
-    pub const PHY_REG_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data
-
-    pub const PHY_REG_WUCSR: u16 = 0x8010;
-
-    pub const PHY_REG_BCR_COLTEST: u16 = 1 << 7;
-    pub const PHY_REG_BCR_FD: u16 = 1 << 8;
-    pub const PHY_REG_BCR_ANRST: u16 = 1 << 9;
-    pub const PHY_REG_BCR_ISOLATE: u16 = 1 << 10;
-    pub const PHY_REG_BCR_POWERDN: u16 = 1 << 11;
-    pub const PHY_REG_BCR_AN: u16 = 1 << 12;
-    pub const PHY_REG_BCR_100M: u16 = 1 << 13;
-    pub const PHY_REG_BCR_LOOPBACK: u16 = 1 << 14;
-    pub const PHY_REG_BCR_RESET: u16 = 1 << 15;
-
-    pub const PHY_REG_BSR_JABBER: u16 = 1 << 1;
-    pub const PHY_REG_BSR_UP: u16 = 1 << 2;
-    pub const PHY_REG_BSR_FAULT: u16 = 1 << 4;
-    pub const PHY_REG_BSR_ANDONE: u16 = 1 << 5;
-
-    pub const PHY_REG_SSR_ANDONE: u16 = 1 << 12;
-    pub const PHY_REG_SSR_SPEED: u16 = 0b111 << 2;
-    pub const PHY_REG_SSR_10BASE_HD: u16 = 0b001 << 2;
-    pub const PHY_REG_SSR_10BASE_FD: u16 = 0b101 << 2;
-    pub const PHY_REG_SSR_100BASE_HD: u16 = 0b010 << 2;
-    pub const PHY_REG_SSR_100BASE_FD: u16 = 0b110 << 2;
-}
-use self::phy_consts::*;
-
-const EMAC_DES3_OWN: u32 = 0x8000_0000;
-const EMAC_DES3_CTXT: u32 = 0x4000_0000;
-const EMAC_DES3_FD: u32 = 0x2000_0000;
-const EMAC_DES3_LD: u32 = 0x1000_0000;
-const EMAC_DES3_ES: u32 = 0x0000_8000;
-const EMAC_TDES2_IOC: u32 = 0x8000_0000;
-const EMAC_RDES3_IOC: u32 = 0x4000_0000;
-const EMAC_RDES3_PL: u32 = 0x0000_7FFF;
-const EMAC_RDES3_BUF1V: u32 = 0x0100_0000;
-const EMAC_TDES2_B1L: u32 = 0x0000_3FFF;
-const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF;
-
-// 6 DMAC, 6 SMAC, 4 q tag, 2 ethernet type II, 1500 ip MTU, 4 CRC, 2 padding
-const ETH_BUFFER_SIZE: usize = 1524;
-const ETH_DESC_U32_SIZE: usize = 4;
-const ETH_TX_BUFFER_COUNT: usize = 4;
-const ETH_RX_BUFFER_COUNT: usize = 4;
-
-#[allow(dead_code)]
-mod cr_consts {
-    /* For HCLK 60-100 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_42: u8 = 0;
-    /* For HCLK 100-150 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_62: u8 = 1;
-    /* For HCLK 20-35 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_16: u8 = 2;
-    /* For HCLK 35-60 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_26: u8 = 3;
-    /* For HCLK 150-250 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_102: u8 = 4;
-    /* For HCLK 250-300 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_124: u8 = 5;
-}
-use self::cr_consts::*;
-
-// set clock range in MAC MII address register
-// 200 MHz AHB clock = eth_hclk
-const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
-
-const PHY_ADDR: u8 = 0;
-
-fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 {
-    while mac.macmdioar.read().mb().bit_is_set() {}
-    mac.macmdioar.modify(|_, w| unsafe {
-        w.pa()
-            .bits(PHY_ADDR)
-            .rda()
-            .bits(reg_addr)
-            .goc()
-            .bits(0b11) // read
-            .cr()
-            .bits(CLOCK_RANGE)
-            .mb()
-            .set_bit()
-    });
-    while mac.macmdioar.read().mb().bit_is_set() {}
-    mac.macmdiodr.read().md().bits()
-}
-
-fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) {
-    while mac.macmdioar.read().mb().bit_is_set() {}
-    mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) });
-    mac.macmdioar.modify(|_, w| unsafe {
-        w.pa()
-            .bits(PHY_ADDR)
-            .rda()
-            .bits(reg_addr)
-            .goc()
-            .bits(0b01) // write
-            .cr()
-            .bits(CLOCK_RANGE)
-            .mb()
-            .set_bit()
-    });
-    while mac.macmdioar.read().mb().bit_is_set() {}
-}
-
-// Writes a value to an extended PHY register in MMD address space
-fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) {
-    phy_write(PHY_REG_CTL, 0x0003, mac); // set address
-    phy_write(PHY_REG_ADDAR, reg_addr, mac);
-    phy_write(PHY_REG_CTL, 0x4003, mac); // set data
-    phy_write(PHY_REG_ADDAR, reg_data, mac);
-}
-
-#[repr(align(4))]
-struct RxRing {
-    desc_buf: [[u32; ETH_DESC_U32_SIZE]; ETH_RX_BUFFER_COUNT],
-    pkt_buf: [[u8; ETH_BUFFER_SIZE]; ETH_RX_BUFFER_COUNT],
-    cur_desc: usize,
-}
-
-impl RxRing {
-    const fn new() -> Self {
-        Self {
-            desc_buf: [[0; ETH_DESC_U32_SIZE]; ETH_RX_BUFFER_COUNT],
-            pkt_buf: [[0; ETH_BUFFER_SIZE]; ETH_RX_BUFFER_COUNT],
-            cur_desc: 0,
-        }
-    }
-
-    unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
-        assert_eq!(self.desc_buf[0].len() % 4, 0);
-        assert_eq!(self.pkt_buf[0].len() % 4, 0);
-
-        for i in 0..self.desc_buf.len() {
-            for j in 0..self.desc_buf[0].len() {
-                self.desc_buf[i][j] = 0;
-            }
-            for j in 0..self.pkt_buf[0].len() {
-                self.pkt_buf[i][j] = 0;
-            }
-        }
-
-        let addr = &self.desc_buf as *const _ as u32;
-        assert_eq!(addr & 0x3, 0);
-        dma.dmacrx_dlar.write(|w| w.bits(addr));
-        dma.dmacrx_rlr
-            .write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1));
-
-        self.cur_desc = 0;
-        for _ in 0..self.desc_buf.len() {
-            self.buf_release()
-        }
-    }
-
-    fn next_desc(&self) -> usize {
-        (self.cur_desc + 1) % self.desc_buf.len()
-    }
-
-    // not owned by DMA
-    fn buf_owned(&self) -> bool {
-        self.desc_buf[self.cur_desc][3] & EMAC_DES3_OWN == 0
-    }
-
-    fn buf_valid(&self) -> bool {
-        self.desc_buf[self.cur_desc][3]
-            & (EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_ES | EMAC_DES3_CTXT)
-            == (EMAC_DES3_FD | EMAC_DES3_LD)
-    }
-
-    unsafe fn buf_as_slice_mut<'a>(&self) -> &'a mut [u8] {
-        let len = (self.desc_buf[self.cur_desc][3] & EMAC_RDES3_PL) as usize;
-        let len = cmp::min(len, ETH_BUFFER_SIZE);
-        let addr = &self.pkt_buf[self.cur_desc] as *const _ as *mut u8;
-        slice::from_raw_parts_mut(addr, len)
-    }
-
-    fn buf_release(&mut self) {
-        let addr = &self.pkt_buf[self.cur_desc] as *const _;
-        self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP;
-        self.desc_buf[self.cur_desc][3] =
-            EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN;
-
-        let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
-        assert_eq!(addr & 0x3, 0);
-
-        let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
-
-        // Ensure changes to the descriptor (in particular, the OWN flag) are
-        // committed before DMA engine sees tail pointer store.
-        cortex_m::asm::dsb();
-
-        dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) });
-
-        self.cur_desc = self.next_desc();
-    }
-}
-
-#[repr(align(4))]
-struct TxRing {
-    desc_buf: [[u32; ETH_DESC_U32_SIZE]; ETH_TX_BUFFER_COUNT],
-    pkt_buf: [[u8; ETH_BUFFER_SIZE]; ETH_TX_BUFFER_COUNT],
-    cur_desc: usize,
-}
-
-impl TxRing {
-    const fn new() -> Self {
-        Self {
-            desc_buf: [[0; ETH_DESC_U32_SIZE]; ETH_TX_BUFFER_COUNT],
-            pkt_buf: [[0; ETH_BUFFER_SIZE]; ETH_TX_BUFFER_COUNT],
-            cur_desc: 0,
-        }
-    }
-
-    unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
-        assert_eq!(self.desc_buf[0].len() % 4, 0);
-        assert_eq!(self.pkt_buf[0].len() % 4, 0);
-
-        for i in 0..self.desc_buf.len() {
-            for j in 0..self.desc_buf[0].len() {
-                self.desc_buf[i][j] = 0;
-            }
-            for j in 0..self.pkt_buf[0].len() {
-                self.pkt_buf[i][j] = 0;
-            }
-        }
-        self.cur_desc = 0;
-
-        let addr = &self.desc_buf as *const _ as u32;
-        assert_eq!(addr & 0x3, 0);
-        dma.dmactx_dlar.write(|w| w.bits(addr));
-        dma.dmactx_rlr
-            .write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1));
-        let addr = &self.desc_buf[0] as *const _ as u32;
-        assert_eq!(addr & 0x3, 0);
-        dma.dmactx_dtpr.write(|w| w.bits(addr));
-    }
-
-    fn next_desc(&self) -> usize {
-        (self.cur_desc + 1) % self.desc_buf.len()
-    }
-
-    // not owned by DMA
-    fn buf_owned(&self) -> bool {
-        self.desc_buf[self.cur_desc][3] & EMAC_DES3_OWN == 0
-    }
-
-    unsafe fn buf_as_slice_mut<'a>(&mut self, len: usize) -> &'a mut [u8] {
-        let len = cmp::min(len, ETH_BUFFER_SIZE);
-        self.desc_buf[self.cur_desc][2] =
-            EMAC_TDES2_IOC | (len as u32 & EMAC_TDES2_B1L);
-        let addr = &self.pkt_buf[self.cur_desc] as *const _ as *mut u8;
-        self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP;
-        slice::from_raw_parts_mut(addr, len)
-    }
-
-    fn buf_release(&mut self) {
-        self.desc_buf[self.cur_desc][3] =
-            EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD;
-        self.cur_desc = self.next_desc();
-
-        let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
-        assert_eq!(addr & 0x3, 0);
-
-        let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
-
-        // Ensure packet contents as well as changes to the descriptor have been
-        // committed before DMA engine sees the tail pointer store.
-        cortex_m::asm::dsb();
-
-        dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) });
-    }
-}
-
-pub struct Device {
-    rx: RxRing,
-    tx: TxRing,
-}
-
-impl Device {
-    pub const fn new() -> Self {
-        Self {
-            rx: RxRing::new(),
-            tx: TxRing::new(),
-        }
-    }
-
-    // Initialize the ethernet peripherals
-    //
-    // # Safety
-    //
-    // This iis transitively unsafe since it sets potentially
-    // unsafe register values. Might ultimately be safe if the values
-    // are correct.
-    //
-    // After `init` is called, `Device` shall not be moved.
-    pub unsafe fn init(
-        &mut self,
-        mac: EthernetAddress,
-        eth_mac: &pac::ETHERNET_MAC,
-        eth_dma: &pac::ETHERNET_DMA,
-        eth_mtl: &pac::ETHERNET_MTL,
-    ) {
-        eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
-        while eth_dma.dmamr.read().swr().bit_is_set() {}
-
-        // 200 MHz
-        eth_mac
-            .mac1ustcr
-            .modify(|_, w| w.tic_1us_cntr().bits(200 - 1));
-
-        // Configuration Register
-        eth_mac.maccr.modify(|_, w| {
-            w.arpen()
-                .clear_bit()
-                .ipc()
-                .set_bit()
-                .ipg()
-                .bits(0b000) // 96 bit
-                .ecrsfd()
-                .clear_bit()
-                .dcrs()
-                .clear_bit()
-                .bl()
-                .bits(0b00) // 19
-                .prelen()
-                .bits(0b00) // 7
-                // CRC stripping for Type frames
-                .cst()
-                .set_bit()
-                // Fast Ethernet speed
-                .fes()
-                .set_bit()
-                // Duplex mode
-                .dm()
-                .set_bit()
-                // Automatic pad/CRC stripping
-                .acs()
-                .set_bit()
-                // Retry disable in half-duplex mode
-                .dr()
-                .set_bit()
-        });
-        eth_mac.macecr.modify(|_, w| {
-            w.eipgen()
-                .clear_bit()
-                .usp()
-                .clear_bit()
-                .spen()
-                .clear_bit()
-                .dcrcc()
-                .clear_bit()
-        });
-        // Set the MAC address
-        eth_mac.maca0lr.write(|w| {
-            w.addrlo().bits(
-                u32::from(mac.0[0])
-                    | (u32::from(mac.0[1]) << 8)
-                    | (u32::from(mac.0[2]) << 16)
-                    | (u32::from(mac.0[3]) << 24),
-            )
-        });
-        eth_mac.maca0hr.write(|w| {
-            w.addrhi()
-                .bits(u16::from(mac.0[4]) | (u16::from(mac.0[5]) << 8))
-        });
-        // frame filter register
-        eth_mac.macpfr.modify(|_, w| {
-            w.dntu()
-                .clear_bit()
-                .ipfe()
-                .clear_bit()
-                .vtfe()
-                .clear_bit()
-                .hpf()
-                .clear_bit()
-                .saf()
-                .clear_bit()
-                .saif()
-                .clear_bit()
-                .pcf()
-                .bits(0b00)
-                .dbf()
-                .clear_bit()
-                .pm()
-                .clear_bit()
-                .daif()
-                .clear_bit()
-                .hmc()
-                .clear_bit()
-                .huc()
-                .clear_bit()
-                // Receive All
-                .ra()
-                .clear_bit()
-                // Promiscuous mode
-                .pr()
-                .clear_bit()
-        });
-        eth_mac.macwtr.write(|w| w.pwe().clear_bit());
-        // Flow Control Register
-        eth_mac.macqtx_fcr.modify(|_, w| {
-            // Pause time
-            w.pt().bits(0x100)
-        });
-        eth_mac.macrx_fcr.modify(|_, w| w);
-        eth_mtl.mtlrx_qomr.modify(|_, w| {
-            w
-                // Receive store and forward
-                .rsf()
-                .set_bit()
-                // Dropping of TCP/IP checksum error frames disable
-                .dis_tcp_ef()
-                .clear_bit()
-                // Forward error frames
-                .fep()
-                .clear_bit()
-                // Forward undersized good packets
-                .fup()
-                .clear_bit()
-        });
-        eth_mtl.mtltx_qomr.modify(|_, w| {
-            w
-                // Transmit store and forward
-                .tsf()
-                .set_bit()
-        });
-
-        if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007)
-            | (phy_read(PHY_REG_ID2, eth_mac) != 0xC131)
-        {
-            error!("PHY ID error!");
-        }
-
-        phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac);
-        while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET
-            == PHY_REG_BCR_RESET
-        {}
-        phy_write_ext(PHY_REG_WUCSR, 0, eth_mac);
-        phy_write(
-            PHY_REG_BCR,
-            PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
-            eth_mac,
-        );
-        /*
-        while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {};
-        while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {};
-        while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED)
-            != PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {};
-        */
-
-        // operation mode register
-        eth_dma.dmamr.modify(|_, w| {
-            w.intm()
-                .bits(0b00)
-                // Rx Tx priority ratio 1:1
-                .pr()
-                .bits(0b000)
-                .txpr()
-                .clear_bit()
-                .da()
-                .clear_bit()
-        });
-        // bus mode register
-        eth_dma.dmasbmr.modify(|_, w| {
-            // Address-aligned beats
-            w.aal()
-                .set_bit()
-                // Fixed burst
-                .fb()
-                .set_bit()
-        });
-        eth_dma
-            .dmaccr
-            .modify(|_, w| w.dsl().bits(0).pblx8().clear_bit().mss().bits(536));
-        eth_dma.dmactx_cr.modify(|_, w| {
-            w
-                // Tx DMA PBL
-                .txpbl()
-                .bits(32)
-                .tse()
-                .clear_bit()
-                // Operate on second frame
-                .osf()
-                .clear_bit()
-        });
-
-        eth_dma.dmacrx_cr.modify(|_, w| {
-            w
-                // receive buffer size
-                .rbsz()
-                .bits(ETH_BUFFER_SIZE as u16)
-                // Rx DMA PBL
-                .rxpbl()
-                .bits(32)
-                // Disable flushing of received frames
-                .rpf()
-                .clear_bit()
-        });
-
-        self.rx.init(eth_dma);
-        self.tx.init(eth_dma);
-
-        // Manage MAC transmission and reception
-        eth_mac.maccr.modify(|_, w| {
-            w.re()
-                .bit(true) // Receiver Enable
-                .te()
-                .bit(true) // Transmiter Enable
-        });
-        eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit());
-
-        // Ensure ring buffer descriptors have been set up in memory before
-        // enabling DMA engine.
-        cortex_m::asm::dsb();
-
-        // Manage DMA transmission and reception
-        eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());
-        eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit());
-
-        eth_dma
-            .dmacsr
-            .modify(|_, w| w.tps().set_bit().rps().set_bit());
-    }
-}
-
-impl<'a, 'b> phy::Device<'a> for &'b mut Device {
-    type RxToken = RxToken<'a>;
-    type TxToken = TxToken<'a>;
-
-    fn capabilities(&self) -> phy::DeviceCapabilities {
-        let mut capabilities = phy::DeviceCapabilities::default();
-        // ethernet frame type II (6 smac, 6 dmac, 2 ethertype),
-        // sans CRC (4), 1500 IP MTU
-        capabilities.max_transmission_unit = 1514;
-        capabilities.max_burst_size = Some(self.tx.desc_buf.len());
-        capabilities
-    }
-
-    fn receive(&mut self) -> Option<(RxToken, TxToken)> {
-        // Skip all queued packets with errors.
-        while self.rx.buf_owned() && !self.rx.buf_valid() {
-            self.rx.buf_release()
-        }
-
-        if !(self.rx.buf_owned() && self.tx.buf_owned()) {
-            return None;
-        }
-
-        Some((RxToken(&mut self.rx), TxToken(&mut self.tx)))
-    }
-
-    fn transmit(&mut self) -> Option<TxToken> {
-        if !self.tx.buf_owned() {
-            return None;
-        }
-
-        Some(TxToken(&mut self.tx))
-    }
-}
-
-pub struct RxToken<'a>(&'a mut RxRing);
-
-impl<'a> phy::RxToken for RxToken<'a> {
-    fn consume<R, F>(self, _timestamp: Instant, f: F) -> Result<R>
-    where
-        F: FnOnce(&mut [u8]) -> Result<R>,
-    {
-        let result = f(unsafe { self.0.buf_as_slice_mut() });
-        self.0.buf_release();
-        result
-    }
-}
-
-pub struct TxToken<'a>(&'a mut TxRing);
-
-impl<'a> phy::TxToken for TxToken<'a> {
-    fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R>
-    where
-        F: FnOnce(&mut [u8]) -> Result<R>,
-    {
-        let result = f(unsafe { self.0.buf_as_slice_mut(len) });
-        self.0.buf_release();
-        result
-    }
-}
diff --git a/src/pounder/attenuators.rs b/src/pounder/attenuators.rs
deleted file mode 100644
index d9785f8..0000000
--- a/src/pounder/attenuators.rs
+++ /dev/null
@@ -1,57 +0,0 @@
-use super::error::Error;
-use super::DdsChannel;
-
-pub trait AttenuatorInterface {
-    fn modify(&mut self, attenuation: f32, channel: DdsChannel) -> Result<f32, Error> {
-        if attenuation > 31.5 || attenuation < 0.0 {
-            return Err(Error::Bounds);
-        }
-
-        // Calculate the attenuation code to program into the attenuator. The attenuator uses a
-        // code where the LSB is 0.5 dB.
-        let attenuation_code = (attenuation * 2.0) as u8;
-
-        // Read all the channels, modify the channel of interest, and write all the channels back.
-        // This ensures the staging register and the output register are always in sync.
-        let mut channels = [0_u8; 4];
-        self.read_all(&mut channels)?;
-
-        // The lowest 2 bits of the 8-bit shift register on the attenuator are ignored. Shift the
-        // attenuator code into the upper 6 bits of the register value. Note that the attenuator
-        // treats inputs as active-low, so the code is inverted before writing.
-        channels[channel as usize] = !attenuation_code.wrapping_shl(2);
-        self.write_all(&channels)?;
-
-        // Finally, latch the output of the updated channel to force it into an active state.
-        self.latch(channel)?;
-
-        Ok(attenuation_code as f32 / 2.0)
-    }
-
-    fn read(&mut self, channel: DdsChannel) -> Result<f32, Error> {
-        let mut channels = [0_u8; 4];
-
-        // Reading the data always shifts data out of the staging registers, so we perform a
-        // duplicate write-back to ensure the staging register is always equal to the output
-        // register.
-        self.read_all(&mut channels)?;
-        self.write_all(&channels)?;
-
-        // The attenuation code is stored in the upper 6 bits of the register, where each LSB
-        // represents 0.5 dB. The attenuator stores the code as active-low, so inverting the result
-        // (before the shift) has the affect of transforming the bits of interest (and the
-        // dont-care bits) into an active-high state and then masking off the don't care bits. If
-        // the shift occurs before the inversion, the upper 2 bits (which would then be don't
-        // care) would contain erroneous data.
-        let attenuation_code = (!channels[channel as usize]).wrapping_shr(2);
-
-        // Convert the desired channel code into dB of attenuation.
-        Ok(attenuation_code as f32 / 2.0)
-    }
-
-    fn reset(&mut self) -> Result<(), Error>;
-
-    fn latch(&mut self, channel: DdsChannel) -> Result<(), Error>;
-    fn read_all(&mut self, channels: &mut [u8; 4]) -> Result<(), Error>;
-    fn write_all(&mut self, channels: &[u8; 4]) -> Result<(), Error>;
-}
diff --git a/src/pounder/error.rs b/src/pounder/error.rs
deleted file mode 100644
index b3cc596..0000000
--- a/src/pounder/error.rs
+++ /dev/null
@@ -1,11 +0,0 @@
-#[derive(Debug)]
-pub enum Error {
-    Spi,
-    I2c,
-    DDS,
-    Qspi,
-    Bounds,
-    InvalidAddress,
-    InvalidChannel,
-    Adc,
-}
diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs
deleted file mode 100644
index d1f445b..0000000
--- a/src/pounder/mod.rs
+++ /dev/null
@@ -1,264 +0,0 @@
-use mcp23017;
-use ad9959;
-
-mod error;
-pub mod attenuators;
-mod rf_power;
-pub mod types;
-
-use super::hal;
-
-pub use error::Error;
-use attenuators::AttenuatorInterface;
-use types::{DdsChannel, InputChannel};
-use rf_power::PowerMeasurementInterface;
-
-use embedded_hal::{
-    blocking::spi::Transfer,
-    adc::OneShot
-};
-
-#[allow(dead_code)]
-const OSC_EN_N_PIN: u8 = 8 + 7;
-
-const EXT_CLK_SEL_PIN: u8 = 8 + 6;
-
-const ATT_RST_N_PIN: u8 = 8 + 5;
-
-const ATT_LE0_PIN: u8 = 8 + 0;
-const ATT_LE1_PIN: u8 = 8 + 1;
-const ATT_LE2_PIN: u8 = 8 + 2;
-const ATT_LE3_PIN: u8 = 8 + 3;
-
-pub struct QspiInterface {
-    pub qspi: hal::qspi::Qspi,
-    mode: ad9959::Mode,
-}
-
-impl QspiInterface {
-    pub fn new(mut qspi: hal::qspi::Qspi) -> Result<Self, Error> {
-        qspi.configure_mode(hal::qspi::QspiMode::FourBit).map_err(|_| Error::Qspi)?;
-        Ok(Self { qspi: qspi, mode: ad9959::Mode::SingleBitTwoWire })
-    }
-}
-
-impl ad9959::Interface for QspiInterface {
-    type Error = Error;
-
-    fn configure_mode(&mut self, mode: ad9959::Mode) -> Result<(), Error> {
-        self.mode = mode;
-
-        Ok(())
-    }
-
-    fn write(&mut self, addr: u8, data: &[u8]) -> Result<(), Error> {
-        if (addr & 0x80) != 0 {
-            return Err(Error::InvalidAddress);
-        }
-
-        // The QSPI interface implementation always operates in 4-bit mode because the AD9959 uses
-        // IO3 as SYNC_IO in some output modes. In order for writes to be successful, SYNC_IO must
-        // be driven low. However, the QSPI peripheral forces IO3 high when operating in 1 or 2 bit
-        // modes. As a result, any writes while in single- or dual-bit modes has to instead write
-        // the data encoded into 4-bit QSPI data so that IO3 can be driven low.
-        match self.mode {
-            ad9959::Mode::SingleBitTwoWire => {
-                // Encode the data into a 4-bit QSPI pattern.
-
-                // In 4-bit mode, we can send 2 bits of address and data per byte transfer. As
-                // such, we need at least 4x more bytes than the length of data. To avoid dynamic
-                // allocation, we assume the maximum transaction length for single-bit-two-wire is
-                // 2 bytes.
-                let mut encoded_data: [u8; 12] = [0; 12];
-
-                if (data.len() * 4) > (encoded_data.len() - 4) {
-                    return Err(Error::Bounds);
-                }
-
-                // Encode the address into the first 4 bytes.
-                for address_bit in 0..8 {
-                    let offset: u8 = {
-                        if address_bit % 2 == 0 {
-                            4
-                        } else {
-                            0
-                        }
-                    };
-
-                    if addr & address_bit != 0 {
-                        encoded_data[(address_bit >> 1) as usize] |= 1 << offset;
-                    }
-                }
-
-                // Encode the data into the remaining bytes.
-                for byte_index in 0..data.len() {
-                    let byte = data[byte_index];
-                    for address_bit in 0..8 {
-                        let offset: u8 = {
-                            if address_bit % 2 == 0 {
-                                4
-                            } else {
-                                0
-                            }
-                        };
-
-                        if byte & address_bit != 0 {
-                            encoded_data[(byte_index + 1) * 4 + (address_bit >> 1) as usize] |= 1 << offset;
-                        }
-                    }
-                }
-
-                let (encoded_address, encoded_payload) = {
-                    let end_index = (1 + data.len()) * 4;
-                    (encoded_data[0], &encoded_data[1..end_index])
-                };
-
-                self.qspi.write(encoded_address, &encoded_payload).map_err(|_| Error::Qspi)
-            },
-            ad9959::Mode::FourBitSerial => {
-                self.qspi.write(addr, &data).map_err(|_| Error::Qspi)
-            },
-            _ => {
-                Err(Error::Qspi)
-            }
-        }
-    }
-
-    fn read(&mut self, addr: u8, mut dest: &mut [u8]) -> Result<(), Error> {
-        if (addr & 0x80) != 0 {
-            return Err(Error::InvalidAddress);
-        }
-
-        // It is not possible to read data from the AD9959 in single bit two wire mode because the
-        // QSPI interface assumes that data is always received on IO1.
-        if self.mode == ad9959::Mode::SingleBitTwoWire {
-            return Err(Error::Qspi);
-        }
-
-        self.qspi.read(0x80_u8 | addr, &mut dest).map_err(|_| Error::Qspi)
-    }
-}
-
-pub struct PounderDevices<DELAY> {
-    pub ad9959: ad9959::Ad9959<QspiInterface,
-                               DELAY,
-                               hal::gpio::gpiog::PG7<hal::gpio::Output<hal::gpio::PushPull>>>,
-    mcp23017: mcp23017::MCP23017<hal::i2c::I2c<hal::stm32::I2C1>>,
-    attenuator_spi: hal::spi::Spi<hal::stm32::SPI1>,
-    adc1: hal::adc::Adc<hal::stm32::ADC1, hal::adc::Enabled>,
-    adc2: hal::adc::Adc<hal::stm32::ADC2, hal::adc::Enabled>,
-    adc1_in_p: hal::gpio::gpiof::PF11<hal::gpio::Analog>,
-    adc2_in_p: hal::gpio::gpiof::PF14<hal::gpio::Analog>,
-}
-
-impl<DELAY> PounderDevices<DELAY>
-where
-    DELAY: embedded_hal::blocking::delay::DelayMs<u8>,
-{
-    pub fn new(mcp23017: mcp23017::MCP23017<hal::i2c::I2c<hal::stm32::I2C1>>,
-               ad9959: ad9959::Ad9959<QspiInterface,
-                                      DELAY,
-                                      hal::gpio::gpiog::PG7<
-                                        hal::gpio::Output<hal::gpio::PushPull>>>,
-               attenuator_spi: hal::spi::Spi<hal::stm32::SPI1>,
-               adc1: hal::adc::Adc<hal::stm32::ADC1, hal::adc::Enabled>,
-               adc2: hal::adc::Adc<hal::stm32::ADC2, hal::adc::Enabled>,
-               adc1_in_p: hal::gpio::gpiof::PF11<hal::gpio::Analog>,
-               adc2_in_p: hal::gpio::gpiof::PF14<hal::gpio::Analog>,
-               ) -> Result<Self, Error> {
-        let mut devices = Self {
-            mcp23017,
-            ad9959,
-            attenuator_spi,
-            adc1,
-            adc2,
-            adc1_in_p,
-            adc2_in_p,
-        };
-
-        // Configure power-on-default state for pounder. All LEDs are on, on-board oscillator
-        // selected, attenuators out of reset.
-        devices.mcp23017.write_gpio(mcp23017::Port::GPIOA, 0xF).map_err(|_| Error::I2c)?;
-        devices.mcp23017.write_gpio(mcp23017::Port::GPIOB,
-                                    1_u8.wrapping_shl(5)).map_err(|_| Error::I2c)?;
-        devices.mcp23017.all_pin_mode(mcp23017::PinMode::OUTPUT).map_err(|_| Error::I2c)?;
-
-        devices.select_onboard_clock()?;
-
-        Ok(devices)
-    }
-
-    pub fn select_external_clock(&mut self, frequency: u32) -> Result<(), Error>{
-        self.mcp23017.digital_write(EXT_CLK_SEL_PIN, true).map_err(|_| Error::I2c)?;
-        self.ad9959.set_clock_frequency(frequency).map_err(|_| Error::DDS)?;
-
-        Ok(())
-    }
-
-    pub fn select_onboard_clock(&mut self) -> Result<(), Error> {
-        self.mcp23017.digital_write(EXT_CLK_SEL_PIN, false).map_err(|_| Error::I2c)?;
-        self.ad9959.set_clock_frequency(100_000_000).map_err(|_| Error::DDS)?;
-
-        Ok(())
-    }
-}
-
-impl<DELAY> AttenuatorInterface for PounderDevices<DELAY>
-{
-    fn reset(&mut self) -> Result<(), Error> {
-        self.mcp23017.digital_write(ATT_RST_N_PIN, true).map_err(|_| Error::I2c)?;
-        // TODO: Measure the I2C transaction speed to the RST pin to ensure that the delay is
-        // sufficient. Document the delay here.
-        self.mcp23017.digital_write(ATT_RST_N_PIN, false).map_err(|_| Error::I2c)?;
-
-        Ok(())
-    }
-
-    fn latch(&mut self, channel: DdsChannel) -> Result<(), Error> {
-        let pin = match channel {
-            DdsChannel::Zero => ATT_LE1_PIN,
-            DdsChannel::One => ATT_LE0_PIN,
-            DdsChannel::Two => ATT_LE3_PIN,
-            DdsChannel::Three => ATT_LE2_PIN,
-        };
-
-        self.mcp23017.digital_write(pin, true).map_err(|_| Error::I2c)?;
-        // TODO: Measure the I2C transaction speed to the RST pin to ensure that the delay is
-        // sufficient. Document the delay here.
-        self.mcp23017.digital_write(pin, false).map_err(|_| Error::I2c)?;
-
-        Ok(())
-    }
-
-    fn read_all(&mut self, channels: &mut [u8; 4]) -> Result<(), Error> {
-        self.attenuator_spi.transfer(channels).map_err(|_| Error::Spi)?;
-
-        Ok(())
-    }
-
-    fn write_all(&mut self, channels: &[u8; 4]) -> Result<(), Error> {
-        let mut result = [0_u8; 4];
-        result.clone_from_slice(channels);
-        self.attenuator_spi.transfer(&mut result).map_err(|_| Error::Spi)?;
-
-        Ok(())
-    }
-}
-
-impl<DELAY> PowerMeasurementInterface for PounderDevices<DELAY> {
-    fn sample_converter(&mut self, channel: InputChannel) -> Result<f32, Error> {
-        let adc_scale = match channel {
-            InputChannel::Zero => {
-                let adc_reading: u32 = self.adc1.read(&mut self.adc1_in_p).map_err(|_| Error::Adc)?;
-                adc_reading as f32 / self.adc1.max_sample() as f32
-            },
-            InputChannel::One => {
-                let adc_reading: u32 = self.adc2.read(&mut self.adc2_in_p).map_err(|_| Error::Adc)?;
-                adc_reading as f32 / self.adc2.max_sample() as f32
-            },
-        };
-
-        // Convert analog percentage to voltage.
-        Ok(adc_scale * 3.3)
-    }
-}
diff --git a/src/pounder/rf_power.rs b/src/pounder/rf_power.rs
deleted file mode 100644
index dd7a3ec..0000000
--- a/src/pounder/rf_power.rs
+++ /dev/null
@@ -1,14 +0,0 @@
-use super::Error;
-use super::InputChannel;
-
-pub trait PowerMeasurementInterface {
-    fn sample_converter(&mut self, channel: InputChannel) -> Result<f32, Error>;
-
-    fn measure_power(&mut self, channel: InputChannel) -> Result<f32, Error> {
-        let analog_measurement = self.sample_converter(channel)?;
-
-        // The AD8363 with VSET connected to VOUT provides an output voltage of 51.7mV / dB at
-        // 100MHz.
-        Ok(analog_measurement / 0.0517)
-    }
-}
diff --git a/src/pounder/types.rs b/src/pounder/types.rs
deleted file mode 100644
index 9938bfe..0000000
--- a/src/pounder/types.rs
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#[allow(dead_code)]
-#[derive(Debug, Copy, Clone)]
-pub enum DdsChannel {
-    Zero,
-    One,
-    Two,
-    Three,
-}
-
-#[allow(dead_code)]
-#[derive(Debug, Copy, Clone)]
-pub enum InputChannel {
-    Zero,
-    One,
-}
diff --git a/stabilizer/Cargo.lock b/stabilizer/Cargo.lock
new file mode 100644
index 0000000..f6e7f56
--- /dev/null
+++ b/stabilizer/Cargo.lock
@@ -0,0 +1,583 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+[[package]]
+name = "ad9959"
+version = "0.1.0"
+source = "git+https://github.com/quartiq/ad9959.git?branch=feature/basic-driver#b45bce3f0dd7a58b5a272b778001dc9422c2c160"
+dependencies = [
+ "bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
+ "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
+]
+
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+
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+ "as-slice 0.1.3 (registry+https://github.com/rust-lang/crates.io-index)",
+]
+
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diff --git a/stabilizer/Cargo.toml b/stabilizer/Cargo.toml
new file mode 100644
index 0000000..7471dd3
--- /dev/null
+++ b/stabilizer/Cargo.toml
@@ -0,0 +1,64 @@
+[package]
+name = "stabilizer"
+version = "0.3.0"
+authors = ["Robert Jördens <rj@quartiq.de>"]
+description = "Firmware for the Sinara Stabilizer board (stm32h743, eth, poe, 2 adc, 2 dac)"
+categories = ["embedded", "no-std", "hardware-support", "science"]
+license = "GPL-3.0-or-later"
+keywords = ["ethernet", "stm32h7", "adc", "dac", "physics"]
+repository = "https://github.com/quartiq/stabilizer"
+readme = "README.md"
+documentation = "https://docs.rs/stabilizer/"
+edition = "2018"
+exclude = [
+	".travis.yml",
+	".gitignore",
+	"doc/",
+	"doc/*"
+]
+
+[badges]
+travis-ci = { repository = "quartiq/stabilizer", branch = "master" }
+maintenance = { status = "experimental" }
+
+[package.metadata.docs.rs]
+features = []
+default-target = "thumbv7em-none-eabihf"
+
+[dependencies]
+cortex-m = { version = "0.6", features = ["const-fn"] }
+cortex-m-rt = { version = "0.6", features = ["device"] }
+cortex-m-log = { version = "0.6", features = ["log-integration"] }
+log = "0.4"
+panic-semihosting = { version = "0.5", optional = true }
+panic-halt = "0.2"
+serde = { version = "1.0", features = ["derive"], default-features = false }
+heapless = { version = "0.5", features = ["serde"] }
+serde-json-core = "0.1"
+cortex-m-rtfm = "0.5"
+embedded-hal = "0.2.3"
+nb = "0.1.2"
+asm-delay = "0.7.0"
+enum-iterator = "0.6.0"
+
+[dependencies.mcp23017]
+git = "https://github.com/mrd0ll4r/mcp23017.git"
+
+[dependencies.smoltcp]
+version = "0.6"
+features = ["ethernet", "proto-ipv4", "socket-tcp", "proto-ipv6"]
+default-features = false
+
+[dependencies.stm32h7-ethernet]
+git = "https://github.com/quartiq/stm32h7-ethernet.git"
+features = ["stm32h743v"]
+
+[dependencies.stm32h7xx-hal]
+path = "../stm32h7xx-hal/"
+features = ["stm32h743v", "rt", "unproven"]
+
+[features]
+semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
+bkpt = [ ]
+nightly = ["cortex-m/inline-asm"]
+
diff --git a/src/afe.rs b/stabilizer/src/afe.rs
similarity index 59%
rename from src/afe.rs
rename to stabilizer/src/afe.rs
index 8dabf06..868c475 100644
--- a/src/afe.rs
+++ b/stabilizer/src/afe.rs
@@ -1,7 +1,10 @@
 use embedded_hal;
 use serde::{Serialize, Deserialize};
 
-#[derive(Copy, Clone, Debug, Serialize, Deserialize)]
+use core::convert::TryFrom;
+use enum_iterator::IntoEnumIterator;
+
+#[derive(Copy, Clone, Debug, Serialize, Deserialize, IntoEnumIterator)]
 pub enum Gain {
     G1 = 0b00,
     G2 = 0b01,
@@ -14,6 +17,20 @@ pub struct ProgrammableGainAmplifier<A0, A1> {
     a1: A1
 }
 
+impl TryFrom<u8> for Gain {
+    type Error = ();
+
+    fn try_from(value: u8) -> Result<Self, Self::Error> {
+        for gain in Gain::into_enum_iter() {
+            if value == gain as u8 {
+                return Ok(gain)
+            }
+        }
+
+        Err(())
+    }
+}
+
 impl<A0, A1> ProgrammableGainAmplifier<A0, A1>
 where
     A0: embedded_hal::digital::v2::StatefulOutputPin,
@@ -44,22 +61,15 @@ where
         }
     }
 
-    pub fn get_gain(&self) -> Gain {
-        let lsb_set = self.a0.is_set_high().unwrap();
-        let msb_set = self.a1.is_set_high().unwrap();
-
-        if msb_set {
-            if lsb_set {
-               Gain::G10
-            } else {
-                Gain::G5
-            }
-        } else {
-            if lsb_set {
-                Gain::G2
-            } else {
-                Gain::G1
-            }
+    pub fn get_gain(&self) -> Result<Gain, ()> {
+        let mut code: u8 = 0;
+        if self.a0.is_set_high().unwrap() {
+            code |= 0b1;
         }
+        if self.a1.is_set_high().unwrap() {
+            code |= 0b10;
+        }
+
+        Gain::try_from(code)
     }
 }
diff --git a/src/eeprom.rs b/stabilizer/src/eeprom.rs
similarity index 100%
rename from src/eeprom.rs
rename to stabilizer/src/eeprom.rs
diff --git a/src/iir.rs b/stabilizer/src/iir.rs
similarity index 100%
rename from src/iir.rs
rename to stabilizer/src/iir.rs
diff --git a/src/main.rs b/stabilizer/src/main.rs
similarity index 72%
rename from src/main.rs
rename to stabilizer/src/main.rs
index ce36e86..a5eee0b 100644
--- a/src/main.rs
+++ b/stabilizer/src/main.rs
@@ -11,7 +11,7 @@
 #[panic_handler]
 #[cfg(all(feature = "nightly", not(feature = "semihosting")))]
 fn panic(_info: &core::panic::PanicInfo) -> ! {
-    let gpiod = unsafe { &*pac::GPIOD::ptr() };
+    let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() };
     gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
     unsafe {
         core::intrinsics::abort();
@@ -27,22 +27,13 @@ extern crate panic_halt;
 #[macro_use]
 extern crate log;
 
-use nb;
-
 // use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
-use asm_delay;
 use rtfm::cyccnt::{Instant, U32Ext};
 use cortex_m_rt::exception;
 use cortex_m;
 use stm32h7xx_hal as hal;
 use stm32h7xx_hal::{
     prelude::*,
-    stm32 as pac,
-};
-
-use heapless::{
-    String,
-    consts::*,
 };
 
 use embedded_hal::{
@@ -52,18 +43,18 @@ use embedded_hal::{
 use stm32h7_ethernet as ethernet;
 use smoltcp as net;
 
+use heapless::{
+    String,
+    consts::*,
+};
+
 #[link_section = ".sram3.eth"]
 static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
 
-mod eth;
-mod pounder;
-mod server;
 mod afe;
-
-mod iir;
-use iir::*;
-
 mod eeprom;
+mod iir;
+mod server;
 
 #[cfg(not(feature = "semihosting"))]
 fn init_log() {}
@@ -103,16 +94,18 @@ static mut NET_STORE: NetStorage = NetStorage {
 
 const SCALE: f32 = ((1 << 15) - 1) as f32;
 
+const SPI_START_CODE: u32 = 0x201;
+
 // static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
 
 const TCP_RX_BUFFER_SIZE: usize = 8192;
 const TCP_TX_BUFFER_SIZE: usize = 8192;
 
-type AFE0 = afe::ProgrammableGainAmplifier<
+type AFE1 = afe::ProgrammableGainAmplifier<
     hal::gpio::gpiof::PF2<hal::gpio::Output<hal::gpio::PushPull>>,
     hal::gpio::gpiof::PF5<hal::gpio::Output<hal::gpio::PushPull>>>;
 
-type AFE1 = afe::ProgrammableGainAmplifier<
+type AFE2 = afe::ProgrammableGainAmplifier<
     hal::gpio::gpiod::PD14<hal::gpio::Output<hal::gpio::PushPull>>,
     hal::gpio::gpiod::PD15<hal::gpio::Output<hal::gpio::PushPull>>>;
 
@@ -167,34 +160,29 @@ macro_rules! route_request {
     }
 }
 
-
 #[rtfm::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtfm::cyccnt::CYCCNT)]
 const APP: () = {
     struct Resources {
-        adc0: hal::spi::Spi<hal::stm32::SPI2>,
-        dac0: hal::spi::Spi<hal::stm32::SPI4>,
-        afe0: AFE0,
-
-        adc1: hal::spi::Spi<hal::stm32::SPI3>,
-        dac1: hal::spi::Spi<hal::stm32::SPI5>,
+        adc1: hal::spi::Spi<hal::stm32::SPI2>,
+        dac1: hal::spi::Spi<hal::stm32::SPI4>,
         afe1: AFE1,
 
+        adc2: hal::spi::Spi<hal::stm32::SPI3>,
+        dac2: hal::spi::Spi<hal::stm32::SPI5>,
+        afe2: AFE2,
+
         eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
 
-        dbg_pin: hal::gpio::gpioc::PC6<hal::gpio::Output<hal::gpio::PushPull>>,
-        dac_pin: hal::gpio::gpiob::PB15<hal::gpio::Output<hal::gpio::PushPull>>,
         timer: hal::timer::Timer<hal::stm32::TIM2>,
         net_interface: net::iface::EthernetInterface<'static, 'static, 'static,
                                                      ethernet::EthernetDMA<'static>>,
         _eth_mac: ethernet::EthernetMAC,
         mac_addr: net::wire::EthernetAddress,
 
-        pounder: pounder::PounderDevices<asm_delay::AsmDelay>,
-
         #[init([[0.; 5]; 2])]
-        iir_state: [IIRState; 2],
-        #[init([IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
-        iir_ch: [IIR; 2],
+        iir_state: [iir::IIRState; 2],
+        #[init([iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
+        iir_ch: [iir::IIR; 2],
     }
 
     #[init]
@@ -223,30 +211,28 @@ const APP: () = {
 
         clocks.rb.d2ccip1r.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
 
-        let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks);
+        let gpioa = dp.GPIOA.split(&mut clocks);
+        let gpiob = dp.GPIOB.split(&mut clocks);
+        let gpioc = dp.GPIOC.split(&mut clocks);
+        let gpiod = dp.GPIOD.split(&mut clocks);
+        let gpioe = dp.GPIOE.split(&mut clocks);
+        let gpiof = dp.GPIOF.split(&mut clocks);
+        let gpiog = dp.GPIOG.split(&mut clocks);
 
-        let gpioa = dp.GPIOA.split(&mut clocks.ahb4);
-        let gpiob = dp.GPIOB.split(&mut clocks.ahb4);
-        let gpioc = dp.GPIOC.split(&mut clocks.ahb4);
-        let gpiod = dp.GPIOD.split(&mut clocks.ahb4);
-        let gpioe = dp.GPIOE.split(&mut clocks.ahb4);
-        let gpiof = dp.GPIOF.split(&mut clocks.ahb4);
-        let gpiog = dp.GPIOG.split(&mut clocks.ahb4);
-
-        let afe0 = {
+        let afe1 = {
             let a0_pin = gpiof.pf2.into_push_pull_output();
             let a1_pin = gpiof.pf5.into_push_pull_output();
             afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
         };
 
-        let afe1 = {
+        let afe2 = {
             let a0_pin = gpiod.pd14.into_push_pull_output();
             let a1_pin = gpiod.pd15.into_push_pull_output();
             afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
         };
 
         // Configure the SPI interfaces to the ADCs and DACs.
-        let adc0_spi = {
+        let adc1_spi = {
             let spi_miso = gpiob.pb14.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
             let spi_sck = gpiob.pb10.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
             let _spi_nss = gpiob.pb9.into_alternate_af5();
@@ -257,8 +243,9 @@ const APP: () = {
                 })
                 .communication_mode(hal::spi::CommunicationMode::Receiver)
                 .manage_cs()
-                .cs_delay(220e-9)
-                .frame_size(16);
+                .transfer_size(1)
+                .frame_size(16)
+                .cs_delay(220e-9);
 
             let mut spi = dp.SPI2.spi(
                     (spi_sck, spi_miso, hal::spi::NoMosi),
@@ -266,12 +253,12 @@ const APP: () = {
                     50.mhz(),
                     &clocks);
 
-            spi.listen(hal::spi::Event::Rxp);
+            spi.listen(hal::spi::Event::Eot);
 
             spi
         };
 
-        let adc1_spi = {
+        let adc2_spi = {
             let spi_miso = gpiob.pb4.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
             let spi_sck = gpioc.pc10.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
             let _spi_nss = gpioa.pa15.into_alternate_af6();
@@ -283,21 +270,24 @@ const APP: () = {
                 })
                 .communication_mode(hal::spi::CommunicationMode::Receiver)
                 .manage_cs()
+                .transfer_size(1)
                 .frame_size(16)
                 .cs_delay(220e-9);
 
-            let spi = dp.SPI3.spi(
+            let mut spi = dp.SPI3.spi(
                     (spi_sck, spi_miso, hal::spi::NoMosi),
                     config,
                     50.mhz(),
                     &clocks);
 
+            spi.listen(hal::spi::Event::Eot);
+
             spi
         };
 
-        let dac0_spi = {
-            let spi_miso = gpioe.pe5.into_alternate_af5();
-            let spi_sck = gpioe.pe2.into_alternate_af5();
+        let dac1_spi = {
+            let spi_miso = gpioe.pe5.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
+            let spi_sck = gpioe.pe2.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
             let _spi_nss = gpioe.pe4.into_alternate_af5();
 
             let config = hal::spi::Config::new(hal::spi::Mode{
@@ -306,15 +296,17 @@ const APP: () = {
                 })
                 .communication_mode(hal::spi::CommunicationMode::Transmitter)
                 .manage_cs()
+                .transfer_size(1)
                 .frame_size(16)
                 .swap_mosi_miso();
 
-            dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 25.mhz(), &clocks)
+            let spi = dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks);
+            spi
         };
 
-        let dac1_spi = {
-            let spi_miso = gpiof.pf8.into_alternate_af5();
-            let spi_sck = gpiof.pf7.into_alternate_af5();
+        let dac2_spi = {
+            let spi_miso = gpiof.pf8.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
+            let spi_sck = gpiof.pf7.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
             let _spi_nss = gpiof.pf6.into_alternate_af5();
 
             let config = hal::spi::Config::new(hal::spi::Mode{
@@ -323,91 +315,13 @@ const APP: () = {
                 })
                 .communication_mode(hal::spi::CommunicationMode::Transmitter)
                 .manage_cs()
+                .transfer_size(1)
                 .frame_size(16)
                 .swap_mosi_miso();
 
-            dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 25.mhz(), &clocks)
-        };
+            let spi = dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks);
 
-        let pounder_devices = {
-            let ad9959 =  {
-                let qspi_interface = {
-                    // Instantiate the QUADSPI pins and peripheral interface.
-                    // TODO: Place these into a pins structure that is provided to the QSPI
-                    // constructor.
-                    let _qspi_clk = gpiob.pb2.into_alternate_af9();
-                    let _qspi_ncs = gpioc.pc11.into_alternate_af9();
-                    let _qspi_io0 = gpioe.pe7.into_alternate_af10();
-                    let _qspi_io1 = gpioe.pe8.into_alternate_af10();
-                    let _qspi_io2 = gpioe.pe9.into_alternate_af10();
-                    let _qspi_io3 = gpioe.pe10.into_alternate_af10();
-
-                    let qspi = hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()).unwrap();
-                    pounder::QspiInterface::new(qspi).unwrap()
-                };
-
-                let mut reset_pin = gpioa.pa0.into_push_pull_output();
-                let io_update = gpiog.pg7.into_push_pull_output();
-
-
-                let asm_delay = {
-                    let frequency_hz = clocks.clocks.c_ck().0;
-                    asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz (frequency_hz))
-                };
-
-                ad9959::Ad9959::new(qspi_interface,
-                                    &mut reset_pin,
-                                    io_update,
-                                    asm_delay,
-                                    ad9959::Mode::FourBitSerial,
-                                    100_000_000).unwrap()
-            };
-
-            let io_expander = {
-                let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
-                let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
-                let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks);
-                mcp23017::MCP23017::default(i2c1).unwrap()
-            };
-
-            let spi = {
-                let spi_mosi = gpiod.pd7.into_alternate_af5();
-                let spi_miso = gpioa.pa6.into_alternate_af5();
-                let spi_sck = gpiog.pg11.into_alternate_af5();
-
-                let config = hal::spi::Config::new(hal::spi::Mode{
-                        polarity: hal::spi::Polarity::IdleHigh,
-                        phase: hal::spi::Phase::CaptureOnSecondTransition,
-                    })
-                    .frame_size(8);
-
-                dp.SPI1.spi((spi_sck, spi_miso, spi_mosi), config, 25.mhz(), &clocks)
-            };
-
-            let adc1 = {
-                let mut adc = dp.ADC1.adc(&mut delay, &mut clocks);
-                adc.calibrate();
-
-                adc.enable()
-            };
-
-            let adc2 = {
-                let mut adc = dp.ADC2.adc(&mut delay, &mut clocks);
-                adc.calibrate();
-
-                adc.enable()
-            };
-
-            let adc1_in_p = gpiof.pf11.into_analog();
-            let adc2_in_p = gpiof.pf14.into_analog();
-
-            pounder::PounderDevices::new(io_expander,
-                                         ad9959,
-                                         spi,
-                                         adc1,
-                                         adc2,
-                                         adc1_in_p,
-                                         adc2_in_p).unwrap()
+            spi
         };
 
         let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
@@ -488,28 +402,34 @@ const APP: () = {
         // Utilize the cycle counter for RTFM scheduling.
         cp.DWT.enable_cycle_counter();
 
-        let mut debug_pin = gpioc.pc6.into_push_pull_output();
-        debug_pin.set_low().unwrap();
+        let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks);
+        dma.configure_m2p_stream(hal::dma::Stream::One,
+                             &SPI_START_CODE as *const _ as u32,
+                             &adc1_spi.spi.cr1 as *const _ as u32,
+                             hal::dma::DMAREQ_ID::TIM2_CH1);
 
-        let mut dac_pin = gpiob.pb15.into_push_pull_output();
-        dac_pin.set_low().unwrap();
+        dma.configure_m2p_stream(hal::dma::Stream::Two,
+                             &SPI_START_CODE as *const _ as u32,
+                             &adc2_spi.spi.cr1 as *const _ as u32,
+                             hal::dma::DMAREQ_ID::TIM2_CH2);
 
         // Configure timer 2 to trigger conversions for the ADC
         let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks);
-        timer2.listen(hal::timer::Event::TimeOut);
+        timer2.configure_channel(hal::timer::Channel::One, 0.25);
+        timer2.configure_channel(hal::timer::Channel::Two, 0.75);
+
+        timer2.listen(hal::timer::Event::ChannelOneDma);
+        timer2.listen(hal::timer::Event::ChannelTwoDma);
 
         init::LateResources {
-            adc0: adc0_spi,
-            dac0: dac0_spi,
             adc1: adc1_spi,
             dac1: dac1_spi,
-            afe0: afe0,
+            adc2: adc2_spi,
+            dac2: dac2_spi,
             afe1: afe1,
+            afe2: afe2,
 
-            dbg_pin: debug_pin,
-            dac_pin: dac_pin,
             timer: timer2,
-            pounder: pounder_devices,
 
             eeprom_i2c: eeprom_i2c,
             net_interface: network_interface,
@@ -518,50 +438,37 @@ const APP: () = {
         }
     }
 
-    #[task(binds = TIM2, resources = [dbg_pin, timer, adc0, adc1])]
-    fn tim2(mut c: tim2::Context) {
-        c.resources.timer.clear_uif_bit();
-        c.resources.dbg_pin.set_high().unwrap();
+    #[task(binds = SPI3, resources = [adc2, dac2, iir_state, iir_ch], priority = 2)]
+    fn spi3(c: spi3::Context) {
+        c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit());
 
-        // Start a SPI transaction on ADC0 and ADC1
-        c.resources.adc0.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
-        c.resources.adc1.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
-
-        c.resources.dbg_pin.set_low().unwrap();
-    }
-
-    #[task(binds = SPI2, resources = [adc0, dac0, adc1, dac1, iir_state, iir_ch, dac_pin], priority = 2)]
-    fn adc_spi(c: adc_spi::Context) {
-        #[cfg(feature = "bkpt")]
-        cortex_m::asm::bkpt();
-
-        c.resources.dac_pin.set_high().unwrap();
-
-        let output_ch1 = {
-            let a: u16 = c.resources.adc0.read().unwrap();
-            let x0 = f32::from(a as i16);
-            let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
-            y0 as i16 as u16 ^ 0x8000
-        };
-        c.resources.adc0.spi.ifcr.write(|w| w.eotc().set_bit());
-
-        let output_ch2 = {
-            let a: u16 = nb::block!(c.resources.adc1.read()).unwrap();
+        let output: u16 = {
+            let a: u16 = c.resources.adc2.read().unwrap();
             let x0 = f32::from(a as i16);
             let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
             y0 as i16 as u16 ^ 0x8000
         };
-        c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit());
 
-        c.resources.dac0.send(output_ch1).unwrap();
-        c.resources.dac1.send(output_ch2).unwrap();
-
-        c.resources.dac_pin.set_low().unwrap();
-        #[cfg(feature = "bkpt")]
-        cortex_m::asm::bkpt();
+        c.resources.dac2.spi.ifcr.write(|w| w.eotc().set_bit().txtfc().set_bit());
+        c.resources.dac2.send(output).unwrap();
     }
 
-    #[idle(resources=[net_interface, mac_addr, iir_state, iir_ch, afe0, afe1])]
+    #[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
+    fn spi2(c: spi2::Context) {
+        c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit());
+
+        let output: u16 = {
+            let a: u16 = c.resources.adc1.read().unwrap();
+            let x0 = f32::from(a as i16);
+            let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
+            y0 as i16 as u16 ^ 0x8000
+        };
+
+        c.resources.dac1.spi.ifcr.write(|w| w.eotc().set_bit().txtfc().set_bit());
+        c.resources.dac1.send(output).unwrap();
+    }
+
+    #[idle(resources=[net_interface, mac_addr, iir_state, iir_ch, afe1, afe2])]
     fn idle(mut c: idle::Context) -> ! {
 
         let mut socket_set_entries: [_; 8] = Default::default();
@@ -569,7 +476,7 @@ const APP: () = {
 
         let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
         let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
-        let tcp_handle0 = {
+        let tcp_handle = {
             let tcp_rx_buffer = net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
             let tcp_tx_buffer = net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
             let tcp_socket = net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
@@ -594,7 +501,7 @@ const APP: () = {
 
             {
                 let socket =
-                    &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle0);
+                    &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle);
                 if socket.state() == net::socket::TcpState::CloseWait {
                     socket.close();
                 } else if !(socket.is_open() || socket.is_listening()) {
@@ -618,26 +525,11 @@ const APP: () = {
 
                                     Ok::<server::Status, ()>(state)
                                 })),
-                                ("stabilizer/afe0/gain", (|| {
-                                    Ok::<afe::Gain, ()>(c.resources.afe0.get_gain())
-                                })),
-                                ("stabilizer/afe1/gain", (|| {
-                                    Ok::<afe::Gain, ()>(c.resources.afe1.get_gain())
-                                }))
+                                ("stabilizer/afe1/gain", (|| c.resources.afe1.get_gain())),
+                                ("stabilizer/afe2/gain", (|| c.resources.afe2.get_gain()))
                             ],
 
                             modifiable_attributes: [
-                                ("stabilizer/iir0/state", server::IirRequest, (|req: server::IirRequest| {
-                                    c.resources.iir_ch.lock(|iir_ch| {
-                                        if req.channel > 1 {
-                                            return Err(());
-                                        }
-
-                                        iir_ch[req.channel as usize] = req.iir;
-
-                                        Ok::<server::IirRequest, ()>(req)
-                                    })
-                                })),
                                 ("stabilizer/iir1/state", server::IirRequest, (|req: server::IirRequest| {
                                     c.resources.iir_ch.lock(|iir_ch| {
                                         if req.channel > 1 {
@@ -649,11 +541,22 @@ const APP: () = {
                                         Ok::<server::IirRequest, ()>(req)
                                     })
                                 })),
-                                ("stabilizer/afe0/gain", afe::Gain, (|gain| {
-                                    Ok::<(), ()>(c.resources.afe0.set_gain(gain))
+                                ("stabilizer/iir2/state", server::IirRequest, (|req: server::IirRequest| {
+                                    c.resources.iir_ch.lock(|iir_ch| {
+                                        if req.channel > 1 {
+                                            return Err(());
+                                        }
+
+                                        iir_ch[req.channel as usize] = req.iir;
+
+                                        Ok::<server::IirRequest, ()>(req)
+                                    })
                                 })),
                                 ("stabilizer/afe1/gain", afe::Gain, (|gain| {
                                     Ok::<(), ()>(c.resources.afe1.set_gain(gain))
+                                })),
+                                ("stabilizer/afe2/gain", afe::Gain, (|gain| {
+                                    Ok::<(), ()>(c.resources.afe2.set_gain(gain))
                                 }))
                             ]
                         )
diff --git a/src/server.rs b/stabilizer/src/server.rs
similarity index 100%
rename from src/server.rs
rename to stabilizer/src/server.rs
diff --git a/stm32h7xx-hal b/stm32h7xx-hal
new file mode 160000
index 0000000..d79cb00
--- /dev/null
+++ b/stm32h7xx-hal
@@ -0,0 +1 @@
+Subproject commit d79cb0015a6f0cbb819907efe3a817f7dce14bab