itcm: add some comments, make it safe
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441c81d135
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@ -105,8 +105,17 @@ pub struct PounderDevices {
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/// Static storage for the ethernet DMA descriptor ring.
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/// Static storage for the ethernet DMA descriptor ring.
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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/// Setup ITCM and load its code from flash
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/// Setup ITCM and load its code from flash.
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unsafe fn setup_itcm() {
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///
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/// For portability and maintainability this is implemented in Rust.
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/// Since this is implemented in Rust the compiler may assume that bss and data are set
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/// up already. There is no easy way to ensure this implementation will never need bss
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/// or data. Hence we can't safely run this as the cortex-m-rt `pre_init` hook before
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/// bss/data is setup.
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///
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/// Calling (through IRQ or directly) any code in ITCM before having called
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/// this method is undefined.
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fn load_itcm() {
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extern "C" {
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extern "C" {
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static mut __sitcm: u32;
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static mut __sitcm: u32;
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static mut __eitcm: u32;
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static mut __eitcm: u32;
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@ -114,18 +123,29 @@ unsafe fn setup_itcm() {
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}
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}
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use core::{ptr, slice, sync::atomic};
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use core::{ptr, slice, sync::atomic};
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// NOTE(unsafe): Assuming the address symbols from the linker as well as
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// the source instruction data are all valid, this is safe as it only
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// copies linker-prepared data to where the code expects it to be.
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// Calling it multiple times is safe as well.
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unsafe {
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// ITCM is enabled on reset on our CPU but might not be on others.
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// ITCM is enabled on reset on our CPU but might not be on others.
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// Keep for completeness.
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// Keep for completeness.
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const ITCMCR: *mut u32 = 0xE000_EF90usize as _;
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const ITCMCR: *mut u32 = 0xE000_EF90usize as _;
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ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1);
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ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1);
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// Ensure ITCM is enabled before loading.
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atomic::fence(atomic::Ordering::SeqCst);
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atomic::fence(atomic::Ordering::SeqCst);
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let len =
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let len =
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(&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize;
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(&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize;
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let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len);
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let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len);
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let src = slice::from_raw_parts(&__siitcm as *const _, len);
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let src = slice::from_raw_parts(&__siitcm as *const _, len);
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// Load code into ITCM.
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dst.copy_from_slice(src);
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dst.copy_from_slice(src);
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}
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// Ensure ITCM is loaded before potentially executing any instructions from it.
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atomic::fence(atomic::Ordering::SeqCst);
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atomic::fence(atomic::Ordering::SeqCst);
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cortex_m::asm::dsb();
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cortex_m::asm::dsb();
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cortex_m::asm::isb();
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cortex_m::asm::isb();
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@ -183,12 +203,12 @@ pub fn setup(
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log::set_logger(&LOGGER)
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log::set_logger(&LOGGER)
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.map(|()| log::set_max_level(log::LevelFilter::Trace))
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.map(|()| log::set_max_level(log::LevelFilter::Trace))
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.unwrap();
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.unwrap();
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log::info!("starting...");
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log::info!("Starting");
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}
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}
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unsafe {
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// Before being able to call any code in ITCM, load that code from flash.
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setup_itcm();
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log::info!("Loading ITCM");
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}
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load_itcm();
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// Set up the system timer for RTIC scheduling.
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// Set up the system timer for RTIC scheduling.
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{
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{
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@ -902,6 +922,7 @@ pub fn setup(
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#[cfg(feature = "pounder_v1_1")]
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#[cfg(feature = "pounder_v1_1")]
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let pounder_stamper = {
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let pounder_stamper = {
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logger::info!("Pounder v1.1 or later");
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let etr_pin = gpioa.pa0.into_alternate_af3();
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let etr_pin = gpioa.pa0.into_alternate_af3();
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// The frequency in the constructor is dont-care, as we will modify the period + clock
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// The frequency in the constructor is dont-care, as we will modify the period + clock
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