From c04180635b9b50e347c8bfba48c9c6370d06c2b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 26 Nov 2020 11:16:08 +0100 Subject: [PATCH] dacs: macros --- src/dac.rs | 427 ++++++++++++++++------------------------------------ src/main.rs | 12 +- 2 files changed, 139 insertions(+), 300 deletions(-) diff --git a/src/dac.rs b/src/dac.rs index d6325c2..7f99001 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -11,306 +11,143 @@ use super::{ // The following global buffers are used for the DAC code DMA transfers. Two buffers are used for // each transfer in a ping-pong buffer configuration (one is being prepared while the other is being // processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on -// startup are undefined. +// startup are undefined. The dimension are `ADC_BUF[adc_index][ping_pong_index][sample_index]`. #[link_section = ".axisram.buffers"] -static mut DAC0_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; +static mut DAC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 2]; 2] = + [[[0; SAMPLE_BUFFER_SIZE]; 2]; 2]; -#[link_section = ".axisram.buffers"] -static mut DAC0_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; - -#[link_section = ".axisram.buffers"] -static mut DAC1_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; - -#[link_section = ".axisram.buffers"] -static mut DAC1_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; - -/// SPI4 is used as a type for indicating a DMA transfer into the SPI4 TX FIFO -struct SPI4 { - spi: hal::spi::Spi, - _channel: sampling_timer::tim2::Channel3, -} - -impl SPI4 { - pub fn new( - _channel: sampling_timer::tim2::Channel3, - spi: hal::spi::Spi, - ) -> Self { - Self { _channel, spi } - } -} - -// Note(unsafe): This is safe because the DMA request line is logically owned by this module. -// Additionally, the SPI is owned by this structure and is known to be configured for u16 word -// sizes. -unsafe impl TargetAddress for SPI4 { - /// SPI2 is configured to operate using 16-bit transfer words. - type MemSize = u16; - - /// SPI4 DMA requests are generated whenever TIM2 CH3 comparison occurs. - const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH3 as u8); - - /// Whenever the DMA request occurs, it should write into SPI4's TX FIFO. - fn address(&self) -> u32 { - &self.spi.inner().txdr as *const _ as u32 - } -} - -/// SPI5 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI5 TX FIFO -struct SPI5 { - _channel: sampling_timer::tim2::Channel4, - spi: hal::spi::Spi, -} - -impl SPI5 { - pub fn new( - _channel: sampling_timer::tim2::Channel4, - spi: hal::spi::Spi, - ) -> Self { - Self { _channel, spi } - } -} - -// Note(unsafe): This is safe because the DMA request line is logically owned by this module. -// Additionally, the SPI is owned by this structure and is known to be configured for u16 word -// sizes. -unsafe impl TargetAddress for SPI5 { - /// SPI5 is configured to operate using 16-bit transfer words. - type MemSize = u16; - - /// SPI5 DMA requests are generated whenever TIM2 CH4 comparison occurs. - const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH4 as u8); - - /// Whenever the DMA request occurs, it should write into SPI5's TX FIFO - fn address(&self) -> u32 { - &self.spi.inner().txdr as *const _ as u32 - } -} - -/// Represents both DAC output channels. -pub struct DacOutputs { - dac0: Dac0Output, - dac1: Dac1Output, -} - -impl DacOutputs { - /// Construct the DAC outputs. - pub fn new(dac0: Dac0Output, dac1: Dac1Output) -> Self { - Self { dac0, dac1 } - } - - /// Borrow the next DAC output buffers to populate the DAC output codes in-place. - /// - /// # Returns - /// (dac0, dac1) where each value is a mutable reference to the output code array for DAC0 and - /// DAC1 respectively. - pub fn prepare_data( - &mut self, - ) -> ( - &mut [u16; SAMPLE_BUFFER_SIZE], - &mut [u16; SAMPLE_BUFFER_SIZE], - ) { - (self.dac0.prepare_buffer(), self.dac1.prepare_buffer()) - } - - /// Enqueue the next DAC output codes for transmission. - /// - /// # Note - /// It is assumed that data was populated using `prepare_data()` before this function is - /// called. - pub fn commit_data(&mut self) { - self.dac0.commit_buffer(); - self.dac1.commit_buffer(); - } -} - -/// Represents data associated with DAC0. -pub struct Dac0Output { - next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, - // Note: SPI TX functionality may not be used from this structure to ensure safety with DMA. - transfer: Transfer< - hal::dma::dma::Stream4, - SPI4, - MemoryToPeripheral, - &'static mut [u16; SAMPLE_BUFFER_SIZE], - >, - first_transfer: bool, -} - -impl Dac0Output { - /// Construct the DAC0 output channel. - /// - /// # Args - /// * `spi` - The SPI interface used to communicate with the ADC. - /// * `stream` - The DMA stream used to write DAC codes over SPI. - /// * `trigger_channel` - The sampling timer output compare channel for update triggers. - pub fn new( - spi: hal::spi::Spi, - stream: hal::dma::dma::Stream4, - trigger_channel: sampling_timer::tim2::Channel3, - ) -> Self { - // Generate DMA events when an output compare of the timer hitting zero (timer roll over) - // occurs. - trigger_channel.listen_dma(); - trigger_channel.to_output_compare(0); - - // The stream constantly writes to the TX FIFO to write new update codes. - let trigger_config = DmaConfig::default() - .memory_increment(true) - .peripheral_increment(false); - - // Listen for any potential SPI error signals, which may indicate that we are not generating - // update codes. - let mut spi = spi.disable(); - spi.listen(hal::spi::Event::Error); - - // Allow the SPI FIFOs to operate using only DMA data channels. - spi.enable_dma_tx(); - - // Enable SPI and start it in infinite transaction mode. - spi.inner().cr1.modify(|_, w| w.spe().set_bit()); - spi.inner().cr1.modify(|_, w| w.cstart().started()); - - // Construct the trigger stream to write from memory to the peripheral. - let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( - stream, - SPI4::new(trigger_channel, spi), - // Note(unsafe): This buffer is only used once and provided for the DMA transfer. - unsafe { &mut DAC0_BUF0 }, - None, - trigger_config, - ); - - Self { - transfer, - // Note(unsafe): This buffer is only used once and provided for the next DMA transfer. - next_buffer: unsafe { Some(&mut DAC0_BUF1) }, - first_transfer: true, - } - } - - /// Mutably borrow the next output buffer to populate it with DAC codes. - pub fn prepare_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] { - self.next_buffer.as_mut().unwrap() - } - - /// Enqueue the next buffer for transmission to the DAC. - /// - /// # Args - /// * `data` - The next data to write to the DAC. - pub fn commit_buffer(&mut self) { - let next_buffer = self.next_buffer.take().unwrap(); - - // If the last transfer was not complete, we didn't write all our previous DAC codes. - // Wait for all the DAC codes to get written as well. - if self.first_transfer { - self.first_transfer = false - } else { - // Note: If a device hangs up, check that this conditional is passing correctly, as - // there is no time-out checks here in the interest of execution speed. - while self.transfer.get_transfer_complete_flag() == false {} +macro_rules! dac_output { + ($name:ident, $index:literal, $data_stream:ident, + $spi:ident, $trigger_channel:ident, $dma_req:ident) => { + /// SPI is used as a type for indicating a DMA transfer into the SPI TX FIFO + struct $spi { + spi: hal::spi::Spi, + _channel: sampling_timer::tim2::$trigger_channel, } - // Start the next transfer. - self.transfer.clear_interrupts(); - let (prev_buffer, _) = - self.transfer.next_transfer(next_buffer).unwrap(); - - self.next_buffer.replace(prev_buffer); - } -} - -/// Represents the data output stream from DAC1. -pub struct Dac1Output { - next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, - transfer: Transfer< - hal::dma::dma::Stream5, - SPI5, - MemoryToPeripheral, - &'static mut [u16; SAMPLE_BUFFER_SIZE], - >, - first_transfer: bool, -} - -impl Dac1Output { - /// Construct a new DAC1 output data stream. - /// - /// # Args - /// * `spi` - The SPI interface connected to DAC1. - /// * `stream` - The DMA stream used to write DAC codes the SPI TX FIFO. - /// * `trigger_channel` - The timer channel used to generate DMA requests for DAC updates. - pub fn new( - spi: hal::spi::Spi, - stream: hal::dma::dma::Stream5, - trigger_channel: sampling_timer::tim2::Channel4, - ) -> Self { - // Generate DMA events when an output compare of the timer hitting zero (timer roll over) - // occurs. - trigger_channel.listen_dma(); - trigger_channel.to_output_compare(0); - - // The trigger stream constantly writes to the TX FIFO to generate DAC updates. - let trigger_config = DmaConfig::default() - .memory_increment(true) - .peripheral_increment(false) - .circular_buffer(true); - - // Listen for any SPI errors, as this may indicate that we are not generating updates on the - // DAC. - let mut spi = spi.disable(); - spi.listen(hal::spi::Event::Error); - - // Allow the SPI FIFOs to operate using only DMA data channels. - spi.enable_dma_tx(); - - // Enable SPI and start it in infinite transaction mode. - spi.inner().cr1.modify(|_, w| w.spe().set_bit()); - spi.inner().cr1.modify(|_, w| w.cstart().started()); - - // Construct the stream to write from memory to the peripheral. - let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( - stream, - SPI5::new(trigger_channel, spi), - // Note(unsafe): This buffer is only used once and provided to the transfer. - unsafe { &mut DAC1_BUF0 }, - None, - trigger_config, - ); - - Self { - // Note(unsafe): This buffer is only used once and provided for the next DMA transfer. - next_buffer: unsafe { Some(&mut DAC1_BUF1) }, - transfer, - first_transfer: true, - } - } - - /// Mutably borrow the next output buffer to populate it with DAC codes. - pub fn prepare_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] { - self.next_buffer.as_mut().unwrap() - } - - /// Enqueue the next buffer for transmission to the DAC. - /// - /// # Args - /// * `data` - The next data to write to the DAC. - pub fn commit_buffer(&mut self) { - let next_buffer = self.next_buffer.take().unwrap(); - - // If the last transfer was not complete, we didn't write all our previous DAC codes. - // Wait for all the DAC codes to get written as well. - if self.first_transfer { - self.first_transfer = false - } else { - // Note: If a device hangs up, check that this conditional is passing correctly, as - // there is no time-out checks here in the interest of execution speed. - while self.transfer.get_transfer_complete_flag() == false {} + impl $spi { + pub fn new( + _channel: sampling_timer::tim2::$trigger_channel, + spi: hal::spi::Spi, + ) -> Self { + Self { _channel, spi } + } } - // Start the next transfer. - self.transfer.clear_interrupts(); - let (prev_buffer, _) = - self.transfer.next_transfer(next_buffer).unwrap(); + // Note(unsafe): This is safe because the DMA request line is logically owned by this module. + // Additionally, the SPI is owned by this structure and is known to be configured for u16 word + // sizes. + unsafe impl TargetAddress for $spi { + /// SPI is configured to operate using 16-bit transfer words. + type MemSize = u16; - self.next_buffer.replace(prev_buffer); - } + /// SPI DMA requests are generated whenever TIM2 CH3 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::$dma_req as u8); + + /// Whenever the DMA request occurs, it should write into SPI's TX FIFO. + fn address(&self) -> u32 { + &self.spi.inner().txdr as *const _ as u32 + } + } + + /// Represents data associated with DAC0. + pub struct $name { + next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, + // Note: SPI TX functionality may not be used from this structure to ensure safety with DMA. + transfer: Transfer< + hal::dma::dma::$data_stream, + $spi, + MemoryToPeripheral, + &'static mut [u16; SAMPLE_BUFFER_SIZE], + >, + first_transfer: bool, + } + + impl $name { + /// Construct the DAC output channel. + /// + /// # Args + /// * `spi` - The SPI interface used to communicate with the ADC. + /// * `stream` - The DMA stream used to write DAC codes over SPI. + /// * `trigger_channel` - The sampling timer output compare channel for update triggers. + pub fn new( + spi: hal::spi::Spi, + stream: hal::dma::dma::$data_stream, + trigger_channel: sampling_timer::tim2::$trigger_channel, + ) -> Self { + // Generate DMA events when an output compare of the timer hitting zero (timer roll over) + // occurs. + trigger_channel.listen_dma(); + trigger_channel.to_output_compare(0); + + // The stream constantly writes to the TX FIFO to write new update codes. + let trigger_config = DmaConfig::default() + .memory_increment(true) + .peripheral_increment(false); + + // Listen for any potential SPI error signals, which may indicate that we are not generating + // update codes. + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_tx(); + + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + // Construct the trigger stream to write from memory to the peripheral. + let transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + stream, + $spi::new(trigger_channel, spi), + // Note(unsafe): This buffer is only used once and provided for the DMA transfer. + unsafe { &mut DAC_BUF[$index][0] }, + None, + trigger_config, + ); + + Self { + transfer, + // Note(unsafe): This buffer is only used once and provided for the next DMA transfer. + next_buffer: unsafe { Some(&mut DAC_BUF[$index][1]) }, + first_transfer: true, + } + } + + /// Mutably borrow the next output buffer to populate it with DAC codes. + pub fn prepare_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] { + self.next_buffer.as_mut().unwrap() + } + + /// Enqueue the next buffer for transmission to the DAC. + /// + /// # Args + /// * `data` - The next data to write to the DAC. + pub fn commit_buffer(&mut self) { + let next_buffer = self.next_buffer.take().unwrap(); + + // If the last transfer was not complete, we didn't write all our previous DAC codes. + // Wait for all the DAC codes to get written as well. + if self.first_transfer { + self.first_transfer = false + } else { + // Note: If a device hangs up, check that this conditional is passing correctly, as + // there is no time-out checks here in the interest of execution speed. + while self.transfer.get_transfer_complete_flag() == false {} + } + + // Start the next transfer. + self.transfer.clear_interrupts(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); + + self.next_buffer.replace(prev_buffer); + } + } + }; } + +dac_output!(Dac0Output, 0, Stream4, SPI4, Channel3, TIM2_CH3); +dac_output!(Dac1Output, 1, Stream5, SPI5, Channel4, TIM2_CH4); diff --git a/src/main.rs b/src/main.rs index 4bf67cf..4dd91e3 100644 --- a/src/main.rs +++ b/src/main.rs @@ -70,7 +70,7 @@ mod sampling_timer; mod server; use adc::{Adc0Input, Adc1Input}; -use dac::{Dac0Output, Dac1Output, DacOutputs}; +use dac::{Dac0Output, Dac1Output}; use dsp::iir; #[cfg(not(feature = "semihosting"))] @@ -189,7 +189,7 @@ const APP: () = { afe1: AFE1, adcs: (Adc0Input, Adc1Input), - dacs: DacOutputs, + dacs: (Dac0Output, Dac1Output), eeprom_i2c: hal::i2c::I2c, @@ -441,7 +441,7 @@ const APP: () = { dma_streams.5, sampling_timer_channels.ch4, ); - DacOutputs::new(dac0, dac1) + (dac0, dac1) }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); @@ -749,7 +749,8 @@ const APP: () = { let adc0_samples = c.resources.adcs.0.transfer_complete_handler(); let adc1_samples = c.resources.adcs.1.transfer_complete_handler(); - let (dac0, dac1) = c.resources.dacs.prepare_data(); + let dac0 = c.resources.dacs.0.prepare_buffer(); + let dac1 = c.resources.dacs.1.prepare_buffer(); for (i, (adc0, adc1)) in adc0_samples.iter().zip(adc1_samples.iter()).enumerate() @@ -769,7 +770,8 @@ const APP: () = { }; } - c.resources.dacs.commit_data(); + c.resources.dacs.0.commit_buffer(); + c.resources.dacs.1.commit_buffer(); } #[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])]