From c030b97714b3027d0e035dc9463b3ca2ba1361a3 Mon Sep 17 00:00:00 2001
From: Ryan Summers <summers.ryan.m@gmail.com>
Date: Tue, 26 Jan 2021 12:49:45 +0100
Subject: [PATCH] Apply suggestions from code review
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Co-authored-by: Robert Jördens <rj@quartiq.de>
---
 src/bin/lockin-internal-demo.rs | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/bin/lockin-internal-demo.rs b/src/bin/lockin-internal-demo.rs
index 113fafd..6acfc36 100644
--- a/src/bin/lockin-internal-demo.rs
+++ b/src/bin/lockin-internal-demo.rs
@@ -41,7 +41,6 @@ const APP: () = {
         #[init(iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE })]
         iir: iir::IIR,
 
-        pll: TimestampHandler,
         lockin: Lockin,
     }
 
@@ -50,13 +49,6 @@ const APP: () = {
         // Configure the microcontroller
         let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device);
 
-        let pll = TimestampHandler::new(
-            4, // relative PLL frequency bandwidth: 2**-4, TODO: expose
-            3, // relative PLL phase bandwidth: 2**-3, TODO: expose
-            ADC_SAMPLE_TICKS_LOG2 as usize,
-            SAMPLE_BUFFER_SIZE_LOG2,
-        );
-
         let lockin = Lockin::new(
             &iir_int::IIRState::default(), // TODO: lowpass, expose
         );
@@ -116,7 +108,8 @@ const APP: () = {
         }
 
         // TODO: Verify that the DAC code is always generated at T=0
-        let (pll_phase, pll_frequency) = c.resources.pll.update(Some(0));
+        let pll_phase = 0i32;
+        let pll_frequency = 1i32 << (32 - 3); // 1/8 of the sample rate
 
         // Harmonic index of the LO: -1 to _de_modulate the fundamental
         let harmonic: i32 = -1;