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Updating ACR to 32-bit

This commit is contained in:
Ryan Summers 2021-04-08 14:58:28 +02:00
parent dd3f293cca
commit bf3dae814d
2 changed files with 8 additions and 8 deletions
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11
ad9959/src/lib.rs
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@ -558,13 +558,14 @@ impl ProfileSerializer {
/// * `channels` - A list of channels to apply the configuration to. /// * `channels` - A list of channels to apply the configuration to.
/// * `ftw` - If provided, indicates a frequency tuning word for the channels. /// * `ftw` - If provided, indicates a frequency tuning word for the channels.
/// * `pow` - If provided, indicates a phase offset word for the channels. /// * `pow` - If provided, indicates a phase offset word for the channels.
/// * `acr` - If provided, indicates the amplitude control register for the channels. /// * `acr` - If provided, indicates the amplitude control register for the channels. The ACR
/// should be stored in the 3 LSB of the word.
pub fn update_channels( pub fn update_channels(
&mut self, &mut self,
channels: &[Channel], channels: &[Channel],
ftw: Option<u32>, ftw: Option<u32>,
pow: Option<u16>, pow: Option<u16>,
acr: Option<u16>, acr: Option<u32>,
) { ) {
let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8); let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8);
for channel in channels.iter() { for channel in channels.iter() {
@ -582,9 +583,7 @@ impl ProfileSerializer {
} }
if let Some(acr) = acr { if let Some(acr) = acr {
let mut data = [0; 3]; self.add_write(Register::ACR, &acr.to_be_bytes()[1..=4]);
data[1..=2].copy_from_slice(&acr.to_be_bytes());
self.add_write(Register::ACR, &data);
} }
} }
@ -608,7 +607,6 @@ impl ProfileSerializer {
// Pad the buffer to 32-bit alignment by adding dummy writes to CSR and LSRR. // Pad the buffer to 32-bit alignment by adding dummy writes to CSR and LSRR.
let padding = 4 - (self.index % 4); let padding = 4 - (self.index % 4);
match padding { match padding {
0 => {}
1 => { 1 => {
// For a pad size of 1, we have to pad with 5 bytes to align things. // For a pad size of 1, we have to pad with 5 bytes to align things.
self.add_write(Register::CSR, &[(self.mode as u8) << 1]); self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
@ -616,6 +614,7 @@ impl ProfileSerializer {
} }
2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]), 2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]),
3 => self.add_write(Register::LSRR, &[0, 0, 0]), 3 => self.add_write(Register::LSRR, &[0, 0, 0]),
4 => {}
_ => unreachable!(), _ => unreachable!(),
} }

5
src/hardware/pounder/dds_output.rs
View File

@ -144,14 +144,15 @@ impl<'a> ProfileBuilder<'a> {
/// * `channels` - A list of channels to apply the configuration to. /// * `channels` - A list of channels to apply the configuration to.
/// * `ftw` - If provided, indicates a frequency tuning word for the channels. /// * `ftw` - If provided, indicates a frequency tuning word for the channels.
/// * `pow` - If provided, indicates a phase offset word for the channels. /// * `pow` - If provided, indicates a phase offset word for the channels.
/// * `acr` - If provided, indicates the amplitude control register for the channels. /// * `acr` - If provided, indicates the amplitude control register for the channels. The
/// 24-bits of the ACR should be stored in the last 3 LSB.
#[allow(dead_code)] #[allow(dead_code)]
pub fn update_channels( pub fn update_channels(
mut self, mut self,
channels: &[Channel], channels: &[Channel],
ftw: Option<u32>, ftw: Option<u32>,
pow: Option<u16>, pow: Option<u16>,
acr: Option<u16>, acr: Option<u32>,
) -> Self { ) -> Self {
self.serializer.update_channels(channels, ftw, pow, acr); self.serializer.update_channels(channels, ftw, pow, acr);
self self